1. Versatile SAT-based Remapping for Standard Cells
Alan Mishchenko and Robert Brayton
UC Berkeley
Thierry Besson, Sriram Govindarajan, Harm Arts and Paul van Besouw
Mentor Graphics

2. Overview Motivation Resynthesis framework SAT-based formulation
SAT vs. other methods in logic synthesis
Experimental results
Conclusion and future work 2

3. Motivation
Improving existing circuit structure is an important task in logic synthesis
An efficient, resource-aware, versatile engine to perform this task is very useful
Applications
AIG (MIG, XOR-MIG, MUX-G, etc) optimization
Resynthesis for mapped networks
Translation of AIG into CNF

4. Previous Work
V. N. Kravets and P. Kudva, “Implicit enumeration of structural changes in circuit optimization”. Proc. DAC’04, pp
Similar approach, based on BDDs
A. Mishchenko and R. Brayton, "SAT-based complete don't-care computation for network optimization", Proc. DATE '05, pp
Early-stage technology-independent optimization
A. Mishchenko, R. Brayton, J.-H. R. Jiang, and S. Jang. "Scalable don't-care-based logic optimization and resynthesis", ACM Trans. Reconfigurable Technology and Systems (TRETS), Vol. 4(4), April 2011, Article 34.
Similar approach, specialized to LUT-based mapping

5. Resynthesis Framework

6. Constructing Boolean Relation of the Node and Candidate Divisors1
Construction steps:
Collect candidate divisors di of node n
Divisors are not in the TFO of n
Their support is a subset of that of node n
Duplicate the window of node n
Use the same output variables
Add inverter for node n in one copy
Create comparator for the outputs
Set the comparator to 1
This is the care set of node n
Convert all gates to CNF … d2 n n d1
How the relation is used:
Function n = F(d1, d2, …) belongs to the relation iff n can be implemented as a gate with function F in terms of divisors d1, d2, …
SAT solver is used to recursively cofactor the relation using different variable orders, resulting in several qualifying functions F X

7. SAT-based Relation Solving
Given Boolean relation in CNF, find contained Boolean function(s)
Pseudo-code
function SolveBR_rec( ordered set of divisors D, assigned divisors A, cnf C ) {
if ( F=1 is UNSAT under assumptions in A ) return 0;
if ( F=0 is UNSAT under assumptions in A ) return 1;
if ( F=di or F=!di for a divisor di in D under assumptions in A ) return di or !di;
d = the topmost variable in D;
return d ? SolveBR_rec( D/d, A  d=1, C ) : SolveBR_rec( D/d, A  d=0, C ); }
functions SolveBR( number of functions N, set of divisors D, cnf C ) {
result = ;
for ( i = 0; i < N; i++ ) {
find a new ordering of divisors in D;
result = result  SolveBR_rec( D, , C );
return result;

8. SAT vs. Other Methods
The presented computations can be implemented with
SAT, ATPG, BDDs, SOPs, truth tables, etc
The implementations differ in terms of
Complexity, resource usage, quality of results, scalability
Based on these metrics, SAT is rated highly
Relatively easy to implement
Relatively inexpensive (both memory and runtime are reasonable)
Good quality of result (typically, there is no clear win)
The most scalable among known engines (the main advantage!)
The main reason why SAT is more scalable than BDDs
BDDs require construction of a canonical form before they can be used
SAT can start working on the problem right away
As a result, SAT has more chances to solve a hard instance

9. Experimental Results
The results explore scalability of the mapper in the context of area-optimization
Using 10 large combinational logic cones
abc 01> r ex02.aig; amap; ps; mfs3 -aev -I 4 -O 2; ps; time; echo
ex : i/o =25237/ lat = nd = edge = area = delay = lev = 13
Library processing: Var = 6. Cell = 71. Fun = Obj = Ave = Skip = 0. Rem = 0. Time = sec
Remapping parameters: TFO = 2. TFI = 4. FanMax = 10. MffcMin = 1. MffcMax = 3. DecMax = 1. 0-cost = no. Effort = yes. Sim = no.
Node = Try = Change = Const0 = 0. Const1 = 0. Buf = 44. Inv = Gate = AndOr = 0. Effort = 962.
MaxDiv = 111. MaxWin = AveDiv = 8. AveWin = Calls = (Sat = Unsat = ) Over = 0. T/O = 0.
Lib = sec ( %)
Win = sec ( %)
Cnf = sec ( %)
Sat = sec ( %)
Sat = sec ( %)
Unsat = sec ( %)
Eval = sec ( %)
Timing = sec ( %)
Other = sec ( %)
ALL = sec ( %)
Cone sizes: 1= =5 3=164 4=34 5=861 6=1 Gate sizes: 1= =897
Reduction: Nodes out of ( %) Edges out of ( %)
ex : i/o =25237/ lat = nd = edge = area = delay = lev = 13

10. Experimental Results
Area-only mapping was performed using a unit-area library.
Parameters of mfs3 were selected to match the runtime of amap and &nf.
Each of these commands took about 3 min for all benchmarks listed.

11. Conclusion Introduced SAT-based network optimization engine
Discussed the key difference between SAT and BDDs
And why SAT replaced BDDs in many application domains
Discussed experimental results
Future work
Improving implementation
Using cubes rather than minterms to improve quality
Using assumption_push/assumption_pop to reduce runtime
Using bookmark/rollback to reduce runtime
Comparing SAT-based vs QBF-based solutions