1. Chap. 8 Datapath Units: Multiplier Design
Prof. An-Yeu Wu
Undergraduate VLSI Design Course
Updated: June 12, 2002

2. Several Implementations of Multipliers
Array Multiplier
2’s Complement Array Multiplier
Serial Multiplier
CSD Code
String-encoding Multiplier
Modified Booth-encoded Multiplier
Implementation (Chap )
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3. 6-by-6 Multiplication
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4. Wallace-Tree Multiplication
FA is a “one’s counter”: Take A, B, and C inputs and encodes them on SUM and CARRY outputs.
A 1-bit full adder (FA) provides a 3:2 compression in the number of bits.
A+B+C=2C+S
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5. 7-bit Wallace tree addition
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6. Ex: 6×6 Wallace Multiplier
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7. Example
In a 32-bit multiplier, the maximum number of partial products is 32 and the compressions are：
32 → 22 → 16 → 12 → 8 → 6 → 4 → 3 → 2
=> There are 9 Full-adder (FA) delays in the array
c.f. Array multiplier (Booth-recoded) =16 partial products to be summed up.
Can be used together with Booth-encoding scheme
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8. Wallace Tree Multiplier
MxN Booth-encoded multiplier (IEEE JSSC, vol.1,no.2, June 1993)
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9. A typical delay distribution of the output of Wallace tree section
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10. Extension 32-bits Wallace-tree multiplier has 9 FA delays in the array
Questions:
For a 64-bit multiplier, what is the minimum adder delay?
Is there any way to reduce the delay by other compression scheme?
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11. Approach: Using 4:2 compression adder
The 4:2 compression (really 5:3) has three XOR delays in the SUM path.
c.f.: Four XOR delays will be present if two adders are used
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12. Referenced Paper
A 54x54 regularly structured tree multiplier: IEEE Journal of Solid-State Circuits (vol. 27, no.9, 1992)
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13. Chap. 8.2.7.2: Implementation of Booth-encoded Multiplier
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14. Implementation: Radix-n Multiplication
Modified Booth-recoding Values
Xi-1 Xi Xi+1 OPERATION NEG ZERO TWO
add
add
sub
add
sub
add
sub
add
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15. 16*16 Booth Multiplier
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16. Array schematic
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17. Array Floorplaning
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18. First Rank Schematic
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19. Booth decoding Schematic
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20. Booth-Add-16 rank floorplan
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21. Adder rank schematic
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22. Booth gate
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23. Array adder layout
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24. Carry Propagate Adder
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25. Homework #6 (Cancelled)
Design an 8-bit Modified Booth-encoded (or String-encoding based) Wallace-tree Multiplier
Draw the schematic diagram of your design.
Verify your design first using C/C++ or Matlab programs.
Write down the Verilog/VHDL code and perform simulation.
Verify your Verilog/VHDL codes. That is,check your simulation results with the C/C++/Matlab results.
Show your (1) Schematic (2) Source code (3) Simulation results in your report.
Due date: June 28, 2002.
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