1. Progress Report
Chester Liu
2014/03/18

2. 01/13 Demonstration Platform
H264-intra encoder
Fix a pipeline bug
Add pipeline stages which can be stalled on multiple paths to improve timing
Forget to add on one path (in ec_code_mb_header.v)
A pulse is dropped if stall signal is asserted at the same cycle
WZ encoder
Both key and WZ use the same input frame
Output only RLC, no CAVLC and CC
Because of buggy FIFO controller
Controller hang if output cannot be stored immediately

3. Revised Encoder Architecture

4. Intel Siskiyou Peak CPU
Simulation manual
Build tool chain and setup simulation environment
Run simulation using the Dhrystone benchmark provided
How to modify C/assembly code and run simulation
Change hardware operation (change XOR to NOT)
Dump waveform control
$fsdbDumpvars(“+mda”)
Dump multidimensional arrays in addition to normal signals
$fsdbDumpvars(“+all”)
Dump all signals (such as SystemVerilog structures) in addition to +mda

5. Schedule Current progress Todo EEPROM controller (and model) done
UART debug interface (and model) done
SPI Wi-Fi controller 90%
Successfully connect to AP
Successfully open TCP socket
Debugging send TCP data
Todo
Fix WZ encoder FIFO bug
Integrate all modules (4/M)