1. EE 584 Homework #1 Inverter Design
Stan McVay
October 15, 2002

2. Schematic Design – Design Architect

3. Digital Simulation – Quicksim II
Confirmed digital functionality of the circuit

4. Layout Design – IC Station

5. Layout Design – Verification and Extraction
DRC Check used several times to find Design Rule violations
LVS Passed after layout was completed:
Parasitic and Distributed extractions completed. Seemed to match well to tutorial (order of magnitude).

6. Analog Simulation - Accusim
Confirmed functionality was correct:

7. Analog Simulation - Accusim
Rise and Fall Times were significantly different than the tutorial values:
These values are about ¼ of the values in the tutorial. Could find no obvious reason for this.