1. CS 152 Computer Architecture & Engineering
Section 9
Spring 2010
Andrew Waterman
University of California, Berkeley

2. Hit rate vs. miss rate, AMAT
One writeup only per group on open-ended

3. Mystery Die DEC Alpha 21264 15M transistors 600 MHz in 350 nm
Highly speculative OoO superscalar

4. Mystery Die Map/IQ FUs Bus FUs FP Map/IQ FPU Bus Fetch I$ D$
DEC Alpha 21264
15M transistors
600 MHz in 350 nm
Highly speculative OoO superscalar
FP Map/IQ
FPU
Bus
Fetch I$ D$

5. Alpha Pipeline

6. Branch Prediction Two kinds of correlating branch predictors:
Local Global
Local History Table
Branch History Table
Branch History Table PC
Global History

7. Branch Prediction 21264 uses both! (tournament predictor) Local Global
Local History Table
Branch History Table
Branch History Table PC
Tournament Predictor
Global History

8. 21264 Fetch
Line/way prediction keeps fetch loop short

9. Alpha Pipeline

10. 21264 Register Renaming
Registers are renamed, then instructions are inserted into the issue queue
Map table backed up on every in-flight insn

11. 21264 Register Renaming What hazards does renaming obviate?
In what situations is renaming useful?
If you had to choose between branch prediction and renaming, which would you pick?

12. 21264 Register Renaming What hazards does renaming obviate?
WAR, WAW
In what situations is renaming useful?
If you had to choose between branch prediction and renaming, which would you pick?

13. 21264 Register Renaming What hazards does renaming obviate?
WAR, WAW
In what situations is renaming useful?
Code with ILP and name dependencies: loops
If you had to choose between branch prediction and renaming, which would you pick?

14. 21264 Register Renaming What hazards does renaming obviate?
WAR, WAW
In what situations is renaming useful?
Code with ILP and name dependencies: loops
If you had to choose between branch prediction and renaming, which would you pick?
Not much ILP within a basic block, so renaming isn’t too useful without branch prediction

15. Alpha Pipeline

16. 21264 Superscalar Execution
The can decode, rename, issue, execute, and commit 4 insns/cycle
How does circuit complexity scale with W in the following operations?
Instruction decode
Register renaming
Result bypassing

17. 21264 Superscalar Execution
The can decode, rename, issue, execute, and commit 4 insns/cycle
How does circuit complexity scale with W in the following operations?
Instruction decode: O(W)
Register renaming
Result bypassing

18. 21264 Superscalar Execution
The can decode, rename, issue, execute, and commit 4 insns/cycle
How does circuit complexity scale with W in the following operations?
Instruction decode: O(W)
Register renaming: O(W2)
Result bypassing

19. 21264 Superscalar Execution
The can decode, rename, issue, execute, and commit 4 insns/cycle
How does circuit complexity scale with W in the following operations?
Instruction decode: O(W)
Register renaming: O(W2)
Result bypassing: O(W2)

20. 21264 Superscalar Execution
The can decode, rename, issue, execute, and commit 4 insns/cycle
How does circuit complexity scale with W in the following operations?
Instruction decode: O(W)
Register renaming: O(W2)
Result bypassing: O(W2)
What about issue window complexity?

21. 21264 Superscalar Execution
21264 couldn’t fit full bypassing into one clock cycle
Instead, they fully bypass within each of two clusters; inter-cluster bypass takes another cycle

22. 21264 Instruction Reordering
As mentioned earlier, uses explicit renaming, as opposed to data-in-ROB design
What does ROB hold?

23. Memory Ordering in the 21264
To execute the critical instruction path quickly, want to execute loads ASAP
Initially, loads speculatively bypass stores
On a misspeculation, set a “wait” bit for that load’s PC, so it will behave conservatively from then on
Clear wait bits periodically

24. Speculation in the 21264 What does the 21264 speculate on?
Next I$ line/way
Branches, indirect jumps
Exceptions
Load/Store ordering
Load hit/miss
Shortens hit time by a cycle
Anything else?