1. Agenda Why simulation Simulation and model Instruction Set model
More Visibility

2. Why Simulation ? Pre-silicon design verification
Hardware and software validation
Flexible by nature
Can be abstracted to represent different levels of accuracy

3. Simulation and model Software model of the processor hardware
Stimulus
Response
Software model of the
processor hardware
Driver logic / Test bench /
Simulator environment

4. Simulation and model Instruction Set Model Debugger / User Interface
Debugger Commands
Logs / messages
Instruction Set Model
Debugger / User Interface

5. Instruction Set Model

6. Instruction set model - characteristics
Needed for DSP/MCU software development and validation
Target users are software developers
Mimics the behavior of the device at the instruction level (programming model)
Correctly models memory accesses, pipeline exceptions and discontinuities, peripheral accesses
Provides visibility to internals through debugger

7. Instruction Set Model - care-abouts
Execution Speed
Cycles/sec, Instruction/sec
Accuracy
Cycle order
Cycle count
Pipeline
CPU/Memory/Peripheral boundary

8. Instruction Set Model - functionality levels
Kernel model (CPU + program/data memory)
Device model (Kernel model + IO memory peripherals)
System model (Device model(s) + shared memory + controller)

9. Instruction Set Model - methodology
Interpreted : Each instruction is decoded and functionality interpreted run-time
Slower, but accurate behavior and debug-friendly
Compiled : The data structures are filled up compile-time
Faster, but difficult to debug
Pre-decodes : Decode is done Once
Binary translation : Target binary to host binary conversion

10. More Visibility
Simulator Analysis
- Cache hit/misses, Stall Analysis
- Events for Count, Break, Profile
Pipeline Visibility
- Knowledge of Pipeline stages, resources,
types of Conflicts