1. VELO readout On detector electronics Off detector electronics to DAQ
signals transported from the detector to a radiation
safe area by ~60m twisted pairs cables
to DAQ
digitization
experiment
"clock"
and controls
High and low voltages
A. Bay electronics

2. Front end chip: Beetle chip
Processing of 128 channels
Has a "pipeline" to store the charge of 160 events
derandomizer
sensor
LHCb clock
multiplexer 32 to 1
Level 0
trigger
decision
output
ch 0
ch 1
ch 2
ch 3
four outputs x 32 = 128 channels
A. Bay electronics

3. Signal on one Beetle output
header
32 channels 4
(32+4)x25= 900 ns => 1.11 MHz max
of L0 trigger in average
25 ns
hit channel
several
events
superposed !
ADC
sample
here
header
A. Bay electronics

4. VELO analogue data transmission
The cable introduces attenuation and
has finite bandwidth:
frequency compensation is done in the
line driver board (2 poles)
cable response and
Spice parametrization
line
driver
spice
data
A. Bay electronics

5. VELO analogue interface
complete
system
The model
data
study of "residuals"
for different frequency
compensation networks
SPICE
residual for a tuned
board is ~2-3%
A. Bay electronics

6. Optical transmission
Digitization done close to the detector. Data transported by optical fibre to counting
house.
A. Bay electronics

7. VELO Repeater bord line driver board output to 60 m line input
from VELO
hybrids
power
regulators
digital
control
A. Bay electronics

8. TELL1 30Gbit/s input data rate 4xGBit Ethernet L1T and HLT
A. Bay electronics

9. LHCb common readout board (TELL1)
Pre-processor FPGA
L1 buffer (58 ms, 58 kevts)
~350 boards being built
Optical or analog interfaces
Credit-card PC
Experiment control system
clock
1 MHz
from FE
electronics
Optical or analog interfaces
CPU
farm
(~1600)
Gigabit ethernet interface
HLT “yes”
storage
2 kHz
Sync & link FPGA
A. Bay electronics

10. Analog-Rx
Optical-Rx
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11. TTC fibre (clock and fast signals)
TELL1 boards under test
Input signals on the
front pannels
Experiment Control
ethernet cable
TTC fibre (clock and fast signals)
Data output to the
computer farm
A. Bay electronics

12. Situation 17 TELL1 have been built and fully tested.
Now production of 30 more boards:
10 already built and are in Lausanne for testing
(boundary scan already done by Barco)
20 more are ready to be mounted by Barco but waiting
for the delivery of a component (DC-DC converter)
320 more boards to be built in 2006.
VELO: boards for full readout of 4 hybrids have been built and are now under test.
Need to tune the line driver gain and frequency response with
the new cable (a cable sample should be at CERN already).
VELO foresees to do a 1/4 of system test during Summer In principle 1/4 of the repeaters, etc., should be ready by then...
CAEN low voltage power sup. under test at CERN (~OK so far).
A. Bay electronics