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Integrated Retiming and Mapping for Sequential Optimization

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Presentation on theme: "Integrated Retiming and Mapping for Sequential Optimization"— Presentation transcript:

1 Integrated Retiming and Mapping for Sequential Optimization
Shauki Elassaad EE290A 11/14/2018 S. Elassaad - EE 290A

2 RTL Flow RTL RTL New Choices Network Logic Transformations Logic
Retiming Met Constraints Tech Mapping Tech Mapping 11/14/2018 S. Elassaad - EE 290A

3 Traditional Synthesis Flow
Given an RTL Netlist Perform a sequence of logic structuring steps. At any step in synthesis, decisions are made and choices are fixed based on some synthesis criteria. Technology mapping of resultant network 11/14/2018 S. Elassaad - EE 290A

4 Proposed Synthesis Flow
AIG to represent the sequential network Peripheral retiming of the network Generate functionally equivalent nodes and stitch them in the logic network. Retiming over all possible logic choices. Technology Mapping of network using the best possible choices. 11/14/2018 S. Elassaad - EE 290A

5 Project Goal Compare area and delay of mapped networks:
New Retiming Algorithm for a Choice-free Fraig Network. Accumulate Choices via a variety of logic transformations. Retiming over all possible logic transformations Technology-mapped network of choice-free logic network Technology-mapped network of logic network with choice nodes attached to it. 11/14/2018 S. Elassaad - EE 290A

6 Choice Nodes Generation
Cuts can be defined by register outputs (primay inputs) and register inputs (primary outputs). Generate choice-nodes for all logic cuts using MVSIS. Accumulate all choices. 11/14/2018 S. Elassaad - EE 290A

7 Choice Node Generation
Original Node 11/14/2018 S. Elassaad - EE 290A

8 Retiming & Mapping Stitch Choices back into AIG
Detect and record different AIG structures of Boolean functions Use them as additional mapping choices to achieve better quality Technology Mapping of resultant network. 11/14/2018 S. Elassaad - EE 290A

9 Sequential Retiming Annotate all choice nodes with sequential arrival times (l-values). Select the best choice for a particular node to be part of final technology-independent network. Min-delay technology mapping Min-area technology mapping 11/14/2018 S. Elassaad - EE 290A

10 Sequential Arrival Times
{l1a,l2a} {l1f} {l1b,l2b} {l1e} {l1c,l2c} {l1d} Choice Node Original Node 11/14/2018 S. Elassaad - EE 290A

11 Experiments Fraig MVSIS Ntk MVSIS Ntk Fraig Fraig FPGA Map FPGA Map
Add Choices Add Choices Add Choices Q1 Retiming Retiming Retime Retiming Retimed Ntk Retimed Ntk Retimed Ntk Q2 Retiming FPGA Map FPGA Map Q3 Q4 11/14/2018 S. Elassaad - EE 290A FPGA Map Q4

12 Results 11/14/2018 S. Elassaad - EE 290A

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