1. Day 33: November 19, 2014 Crosstalk
ESE370: Circuit-Level Modeling, Design, and Optimization for Digital Systems
Day 33: November 19, 2014
Crosstalk
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2. Today Crosstalk How arise Consequences Magnitude Avoiding
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3. Capacitance There are capacitors everywhere Already talked about
Wires as capacitors
Capacitance between terminals on transistor
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4. Miller Effect For an inverting gate
Capacitance between input and output must swing 2 Vhigh
Or…acts as double-sized capacitor
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5. Capacitance Everywhere
Potentially a capacitor between any two conductors
On the chip
On the package
On the board
All wires
Package pins
PCB traces
Cable wires
Bit lines
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6. Capacitor Dependence Decrease with conductor separation
Increase with size
Depends on dielectric
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7. Parallel Wires Parallel-plate capacitance between wires
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8. Wire Capacitance
Changes in voltage on one wire may couple through capacitance to another
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9. Consequences
Qualitative First
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10. Wire step response Step response for isolated wire?
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11. Driven Wire What happens to a driven “victim” wire? One wire switches
Neighbors driven but not switch
What happens to neighbors?
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12. Driven Wire Can this be a problem? What if victim is: Clock line
Asynchronous control
Non-clock used in synchronous system
Outputs sampled at clock edge
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13. Undriven Wire What happens to undriven wire?
Where do we have undriven wires?
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14. Clocked Logic CMOS driven lines Clocked logic
Willing to wait to settle
Impact is solely on delay
May increase delay of transitions
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15. Magnitude
Quantitative
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16. How large is the noise? V1 transitions from 0 to V?
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17. How large is the noise? V1 transitions from 0 to V
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18. Noise Magnitude
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19. SPICE C1=10pF, C2=20pF
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20. Good (?) Capacitance High capacitance to ground plane
Limits node swing from adjacent conductors
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21. Driven Line What happens when victim line is driven?
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22. Driven Line Driven line Recovers with time constant: R2(C1+C2)
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23. Spice: R2=1K, C1=10pF, C2=20pF
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24. Magnitude of Noise on Driven Line
Magnitude of diversion depends on relative time constants
t1<< t2
t1>> t2
t1~= t2
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25. Magnitude of Noise on Driven Line
Magnitude of diversion depends on relative time constants
t1<< t2
full diversion, then recover
t1~= t2
t1>> t2
Charge capacitor faster than line 1 can change
little noise
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26. Spice: C1=1pF, C2=2pF
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27. Switching Line with Finite Drive
What impact does the presence of the non switching line have on the switching line?
All previous questions were about non-switching
Note R on switching
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28. Simultaneous Transition
What happens if lines transition in opposite directions?
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29. Simultaneous Transition
What happens if transition in opposite directions?
Must charge C1 by 2V
Or looks like 2C1 between wires
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30. Simultaneous Transition
What happens if lines transition in same direction?
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31. Simulation V2 switching at ¼ frequency of V1
No crosstalk reference case where no V2
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32. Crosstalk Victim Simulations
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33. Victimization Setup
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34. Crosstalk Victimization Simulation
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35. Where Arise
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36. Cables and PCB Wires
Source;
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37. Printed Circuit Board
Source:
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38. Interconnect Cross Section
Image from Rabaey text, pg48, Fig2-7k
ITRS 2007 38
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39. IC Metalization
Source:
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40. Standard Cell Area inv nand3 All cells uniform height Width of channel
determined
by routing
Cell area
Identify the full custom and standard cell regions on 386DX die
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41. Wires
Will be capacitively coupled to many adjacent wires of varying degrees
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42. bit lines, word lines wordline bitline Penn ESE370 Fall2014 -- DeHon
Source:

43. Addressing
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44. What can we do?
How can we reduce?
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45. What can we do? Orthogonal routing layers Widen spacing between wires
Avoid parallel coupling vertically
Widen spacing between wires
Particularly critical path wires
Limit length two wires run in parallel
Separate with power planes
Separate with ground/power wires
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46. Idea Capacitance is everywhere Especially between adjacent wires
Will get “noise” from crosstalk
Clocked and driven wires
Slow down transitions
Undriven wires voltage changed
Can cause spurious transitions
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47. Admin In lab on Friday Project due Tuesday
Please read lab handout in advance
Project due Tuesday
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