1. Systemarchitecture Dezső Sima Spring 2007 (Ver. 2.1)
 Sima Dezső, 2008

2. Contents 1. Introduction to system architectures
2. The evolution of the system architecture
3. The evolution of Intel’s x86 processor bus
4. Bus innovations introduced in Intel’s P4 chipsets
5. Chipsets of Intel’s P4 family
6. Bandwidth considerations
7. Special aspects of the implementation

3. 1. Introduction to system architectures

4. 1. Introduction Concrete architecture Abstract architecture
Pentium Pro system OS
System level
Pentium Pro
ISA
Pentium Pro
Processor
Processor level
FMUL
Functional unit level
Figure 1.1.: Interpretation of the notion architecture at different levels

5. 2. The evolution of the system architecture

6. 2. The evolution of the system architecture
2.1 System architecture of Intel’s desktop PCs - Overview
System architecture of Intel’s desktop PCs
ISA-based
PCI-based
Port-based
Simple
w/ATA,
USB
w/AGP, ATA,USB
Early
implem.
Recent implem.
8088/80286/ based PCs
486 and early
Pentium based PCs
Mature Pentium based PCs
Early PII
and PIII
based PCs
Mature
PIII/P4
based PCs
P4 Prescott
based PCs
Mature Intel 430
chipsets
Intel 420
chipsets
Intel 440XX
chipsets
Intel 8XX
chipsets
Intel 915X
chipsets
Evolution

7. 2.2 Main steps of the evolution (1)
8088/80286/80386
Processor
Memory/
Main Memory
KBD
Bus controller
(DRAM/FPM)
ISA
Monitor
Adapter WD
Adapter FD
Adapter PP
Adapter SP
Adapter
Multi-I/O card
I/O devices
Figure 2.1: ISA-bus based system architecture
(Used typically in 8088/80286/80386-based PCs)

8. 2.2 Main steps of the evolution (2)
486/Pentium
Processor bus
L2 cache
System
Main Memory
controller
(FPM/EDO)
PCI bus
Peripheral
controller
PCI device
adapter
ISA bus
ISA device
(Legacy and/or
adapter
slow devices)
Figure 2.2: Simple PCI-based system architecture
(Used typically in 486 and early Pentium-based PCs along with Intel 420 and early 430 chipsets)

9. 2.2 Main steps of the evolution (3)
Pentium
Processor bus
L2 cache
System
Main Memory
controller
(FPM/EDO/SDRAM)
PCI bus
IDE/(ATA/33)
IDE port: First on the 430FX (Triton, 1995)
ATA/33: First on the 430TX (1997)
USB: First on the 430VX (Triton III, 1996)
PCI device
adapter
Peripheral
USB
controller
ISA bus
ISA device
adapter
(Legacy and/or
slow devices)
Figure 2.3: PCI-based system architecture with IDE/ATA and USB ports
(Used typically in mature Pentium-based PCs with mature Intel 430 chipsets)

10. 2.2 Main steps of the evolution (4)
PentiumII/
PentiumIII
PentiumII/
PentiumIII
Processor bus
System
AGP
Main Memory
controller
(EDO/SDRAM)
PCI bus
PCI device
adapter
2xIDE/ATA33/66
(Legacy and/or
Peripheral
slow devices)
controller
2xUSB
ISA bus
ISA device
adapter
Figure 2.4: PCI-based system architecture with AGP, IDE/ATA and USB ports
(Used typically in PentiumII and early PentiumIII-based PCs with Intel 440XX chipsets)

11. 2.2 Main steps of the evolution (5)
PentiumIII/
Pentiu4
Processor bus
System
Main Memory
AGP
controller
(SDRAM/)
Hub interface
2xIDE/
LPC
(Used typically in PentiumIII and Pentium4-based systems with Intel 8X0 chipsets)
ATA 33/66/100
Peripheral
Super I/O (KBD, MS, FD, SP, PP, IR)
controller
AC'97
2x/4x USB
PCI bus
PCI device
adapter
PCI to ISA
bridge
ISA bus
ISA device
adapter
(Legacy and/or
slow devices)
Figure 2.5: Early port-based system architecture

12. 2.2 Main steps of the evolution (6)
System
controller
PCI bus
Processor bus
Main Memory
(SDRAM/)
Peripheral
PCI device
adapter
Pentium 4
PCI E.x16
1xIDE/
8x USB
Hub interface
ATA 33/66/100
LPC (KBD, MS, FD, SP, PP, IR)
AC'97
4x SATA
PCI E.x1 (1x/2x)
LAN 10/100
HDAI
Figure 2.6: Recent port-based system architecture

13. 3. The evolution of Intel’s x86 processor bus

14. 3. The evolution of Intel’s x86 processor bus
Main features of the system-bus
Pentium Pro
Width of the
8086
8088
80286
80386
80486
Pentium
PII,
PIII P4
address bus (bit) 20 1 20 1 24 32 2 32 2 32 3 36 36
data bus (bit) 16 1 8 1 16 32 32 64
64+8 4
64+8 4 1
Multiplexed 2
Bits 0,1 not implemented (Doubleword aligned) 3
Bits 0-2 not implemented (Quadword aligned) 4
For error protection
Figure 3.1: Main features of the system-bus

15. 4. Bus innovations introduced into Intel’s P4 chipsets

16. 4. Bus innovations introduced into Intel’s P4 chipsets (1)
11/02
AGP
AGP 8x
5/03
SATA
SATA 1.0a
5/03
PCI
PCI 2.3
2/04
PCI-X
PCI-X 2.2
6/04
PCI Express
PCI Express 1.0a
5/02
USB
USB 2.0
12/01
AC' 97
AC'
6/04
HDAI
HDAI
2001
2002
2003
2004
Figure 4.1: Bus innovations introduced into Intel’s P4 chipsets

17. The principle of the AGP port
4. Bus innovations introduced into Intel’s P4 chipsets (2)
The principle of the AGP port
Processor bus
AGP
Graphic chip
Memory bridge
(North bridge)
Main memory
I/O bridge
Frame buffer
(South bridge)
AGP
Main Features of the AGP port
(Intel)
Version 1.0
Version 2.0
(7/1998)
(5/1998)
(Based on Revision 2.1
(PCI)
of the PCI)
Clock speed
66 MHz
Bus
(Multiplexed 32-bit address bus
Seperate 32-bit address bus
/data bus)
and 32-bit data bus
(Transfer of 4-byte data blocks)
Transfer of 8-byte data blocks
Transfer mode 1x 2x 4x
(AGP-66)
(AGP-133)
(AGP-266)
(double
(quadruple
clocked)
clocked)
Transfer rate
264 MB/s
532 MB/s
1064 MB/s
Figure 4.2.: Early evolution of the AGP port

18. 4. Bus innovations introduced into Intel’s P4 chipsets (3)
ISA
8.33 MHz
8/16-bit
EISA
8.33 MHz
32-bit
PCI
33 MHz
32-bit
PCI v.2
33 MHz
64-bit
PCI v.2.11
33/66 MHz
32/64-bit
PCI v.2.21, 3
33/66 MHz
32/64-bit
PCI v.2.32
33/66 MHz
32/64-bit
1987 88 89 90 91 92 93 94
1995 96 97 98 99
2000 01 02 03
1: Both 3.3 V and 5 V is supported
2: Only 3.3 V is supported
3: Just improving the readibility of the standard text
Figure 4.3: The evolution of the PCI bus standard

19. 4. Bus innovations introduced into Intel’s P4 chipsets (3)
PCI-X v.1.02
66/133 MHz
64-bit
PCI-X v.2.02
266/533 MHz
64-bit
ISA
8.33 MHz
8/16-bit
EISA
8.33 MHz
32-bit
PCI
33 MHz
32-bit
PCI v.2
33 MHz
64-bit
PCI v.2.11
33/66 MHz
32/64-bit
PCI v.2.21, 3
33/66 MHz
32/64-bit
PCI v.2.32
33/66 MHz
32/64-bit
1987 88 89 90 91 92 93 94
1995 96 97 98 99
2000 01 02 03
1: Both 3.3 V and 5 V is supported
2: Only 3.3 V is supported
3: Just improving the readibility of the standard text
Figure 4.4: The introduction of the PCI-X

20. 4. Bus innovations introduced into Intel’s P4 chipsets (5)
Figure 4.5: Slot number limitations of the PCI-X bus
Source: PCI Technology overview, Febr. 2003,

21. 4. Bus innovations introduced into Intel’s P4 chipsets (6)
The PCI Express bus (3GIO)
PCI Express 1.0 introduced in 7/2002
A link consists of 1x, 2x, 4x, 8x, 12x, 16x or 32x signal pairs (lanes) in each direction.
Transfer rate per lane per direction: 2.5 Gbits/s
Encoding 10 bits/byte
Aggreagate bandwidth per lane (in both directions together):
2 x 2,5 /10 = 0,5 Gbyte/s

22. 4. Bus innovations introduced into Intel’s P4 chipsets (7)
ATA (PATA) cable
ATA/PATA and SATA cables
Figure 4.6.: Contrasting ATA/PATA and SATA cables

23. 4. Bus innovations introduced into Intel’s P4 chipsets (8)
AC '97
Version 1.0
Version 2.0
Revision 2.1
Revision 2.2
6/1996: 5 vendors
(9/1997)
(5/1998)
(9/2000)
(Intel, ADI, Creative Labs,
National Semiconductor,
Yamaha).
Link:
5-wire digital
(2 serial data lines)
Audio Codec
16-bit optionally
High Quality audio
18/20-bit AD/DA
(up to 96 KHz sampling rate
resolution
120 dB dynamic range)
48 KHz sampling rate
Modem extension
4 analog stereo inputs
(Cost effective)
2 analog mono inputs
Multiple codec
4/6 channel output
capability
dedicated mic input
(for multichannel
audio solutions etc.)
Digital controller
May reside on any bus
(ISA, PCI, USB, 1394) or
in an I/O-bridge
Figure 4.7.: Early evolution of the AC ’97 bus

24. 4. Bus innovations introduced into Intel’s P4 chipsets (9)
High definition audio (HDA)
AC’97 v.2.2
HDAI
No. of channels 6 8
Resolution
20-bit
32-bit
Sampling rate
96 kHz
192 kHz

25. 4. Bus innovations introduced into Intel’s P4 chipsets (10)
Figure 4.8: Peak bandwidth values and sustained data rates of peripheral buses

26. 5. Chipsets of Intel’s P4 family

27. 5. Chipsets of Intel’s P4 family
5.1 Overview of the P4 family
5.2 Desktop chipsets
5.3 Overview of DP server and workstation chipsets
5.4 DP server chipsets
5.5 DP workstation chipsets

28. 5.1 Overview of the P4 family
11/00
1/02 ^
/42 mtrs m
400 MHz FSB
Northwood-A
Xeon DP line
Desktop-line
Celeron-line
Willamette
1.4/1.5 GHz
(Value PC-s)
On-die 256K L2
/55 mtrs
2A/2.2 GHz
On-die 512K L2
2/02
1.8/2/2.2 GHz
5/01
1.4/1.5/1.7 GHz
On-die 256 K L2
11/02
Prestonia-B
533 MHz FSB
2/2.4/2.6/2.8 GHz
Foster
Prestonia-A
Nocona
2/04
/125mtrs
800 MHz FSB
2.80E/3E/3.20E/3.40E GHz
On-die 1M L2
2000
2001
2002
2003
2004
Xeon - MP line
3/02
/108 mtrs
1.4/1.5/1.6 GHz
Gallatin
/178 mtrs
1.5/1.9/2 GHz
Foster-MP
On-die 512K/1M L3
On-die 1M/2M L3
5/02
Northwood-B
2.26/2.40B/2.53 GHz
Willamette-128
1.7 GHz
6/04
/ 125 mtrs
2.8/3.0/3.2/3.4/3.6 GHz
3.06 GHz
2 GHz
On-die 128K L2
0.18
0.13
9/02
Northwood-128
Cores supporting hyperthreading
5/03
Northwood-C
2.40C/2.60C/2.80C GHz
Cores with EM64T implemented but not enabled
2005
2Q/05
Potomac
0.09
> 3.5 MHz
On-die 8M L3 (?)
Irwindale-C
1Q/05
3.0/3.2/3.4/3.6 GHz
On-die 512K L2, 2M L3
Jayhawk
(Cancelled 5/04)
3.8 GHz
3Q/05
Tejas /
3/04 ^
Gallatin
/286 mtrs m
2.2/2.7/3.0 GHz
On-die 512K L2
On-die 2M/4M L3 m
400 MHz FSB
PGA 603 m
PGA 603 m
PGA 603
7/03 ^
Prestonia-C
/178 mtrs m
3.06 GHz
On-die 512K L2, 1M L3
533 MHz FSB m
PGA 603 m
PGA 603 m
PGA 603 m
PGA 603 m
PGA 604
11/03
11/04 ^ ^
Extreme Edition
Irwindale-A 1
Irwindale-B 1
/178 mtrs m
/178mtrs m
3.2EE GHz
3.4EE GHz
On-die 512K L2, 2M L3
On-die 512K L2, 2 MB L3
800 MHz FSB
1066 MHz FSB m
PGA 478
LGA 775
8/01
6/04
8/04 ^ ^ ^
Willamette
2,3 4 5
Prescott
6,7
Prescott
8,9,10
Prescott-F 11
/42 mtrs m
/125mtrs m
/125mtrs m
GHz
2.8/3.0/3.2/3.4/3.6 GHz
3.20F/3.40F/3.60F GHz
4.0/4.2 GHz
On-die 256K L2
On-die 1M L2
On-die 1M L2
On-die 1M L2
400 MHz FSB
800 MHz FSB
800 MHz FSB
(Cancelled 5/04) m
PGA 423 m
PGA 478 m
PGA 478 m
PGA 478 m
PGA 478 m
PGA 478 m
PGA 478
LGA 775
LGA 775
6/04
9/04 ^ ^
Celeron-D 12
Celeron-D 13
0.09 m
0.09 m
2.4/2.53/2.66/2.8 GHz
2.53/2.66/2.80/2.93 GHz
On-die 256K L2
On-die 256K L2
533 MHz FSB
533 MHz FSB m
PGA 478 m
PGA 478 m
PGA 478
LGA 775
Cores supporting EM64T
Figure 5.1: Intel’s P4 cores (Netburst architecture)

29. 5.2 Desktop chipsets (1)
Cores
11/00
1/02
11/02
2/04
Prescott F
8/04
Willamette
Northwood-A
Northwood-B
Prescott
8/01
5/02
5/03
6/04
Willamette
Northwood-B
Northwood-C
Prescott
FSB
400 MHz
400 MHz
400 MHz
533 MHz
533 MHz
800 MHz
800 MHz
800 MHz
800 MHz HT HT HT HT HT HT
EM64T
EM64T
Socket
PGA 423 m
PGA 478 m
PGA 478 m
PGA 478 m
PGA 478 m
PGA 478 m
PGA 478 m
LGA 775
LGA 775
8/03
Chipsets
848P
10/02
5/03
9/03
5/03
845GV/GE/PE
865G/GV/PE
9/01
5/03
845
865P
5/02
11/01
845 G/E/GL
4/03
845
875P
6/04
9/03
6/04
915G/GV/P
Figure 5.2: Intel’s chipsets designed for P4-based value and desktop PCs

30. 5.2 Desktop chipsets (2)
9/01
5/02
8/03
5/03
4/03
06/04
11/05
845
845xx family
848P
865xx/875P family
915xx family
975x
(Brookdale)
(Springdale/Canterwood)
(Grantsdale)
MCH/GMCH
HT support
no HT
no HT/HT HT HT HT HT
FSB up to
400 MT/s
533 MT/s
800 MT/s
800 MT/s
800 MT/s
1066 MT/s
Nr. of mem. channels
Single channel
Single channel
Single channel
Dual channel
Dual channel
Dual channel
SDR/DDR SDRAM
SDR/DDR SDRAM
DDR SDRAM
DDR SDRAM
DDR2 /DDR SDRAM
DDR2 SDRAM
Memory
(unbuffered)
(unbuffered)
(unbuffered)
(unbuffered)
(unbuffered)
(unbuffered)
Max. memory
2 GB
2 GB
2 GB
4 GB
4 GB
8 GB
DRAM speed up to
DDR 266
DDR 333
DDR 400
DDR 400
DDR 400/DDR2 533
DDR2 667
Additional high speed
CSA
CSA
interface 1
ICH
ICH4:
ICH5/ICH5R:
ICH6/ICH6R:
Graphics interface up to
AGP 4X
AGP 8X
PCI Express x16
ICH2:
ICH7/ICH7R:
ATA up to
Ultra ATA/100
SATA
SATA 1.0a
SATA 1.0a
SATA 1.0a
SATA 1.0a
LAN
10/100 Mbit/s
10/100 Mbit/s
10/100 Mbit/s
10/100 Mbit/s
10/100 Mbit/s
10/100 Mbit/s
PCI
PCI 2.2
PCI 2.2
PCI 2.3
PCI 2.3
PCI 2.3
PCI 2.3
PCI Express x1
PCI Express x1 1.0a 2
PCI Express x1 1.0a 2
USB
USB 1.1
USB 2.0
USB 2.0
USB 2.0
USB 2.0
USB 2.0
AC' 97 3
AC'
AC'
AC'
AC'
AC'
AC'
HDAI 3
HDAI
HDAI 1
The Communications Streaming Architecture (CSA) interface of the MCH provides a link to a Gigabit Ethernet Controller (GbE),
e.g. to Intel's 82547EI GbE controller 2
A GbE controller can be attached via the PCI Express x1 link providing 10/100/1000 Mbit/s speeds. (e.g. Intel's 82571EB
dual channel GbE controller) 3
The Intel High Definition Audio Interface (HDAI) shares pins with the AC '97 link, so these interfaces cannot be
operated concurrently
Figure 5.3: The evolution of Intel’s chipset families designed for P4-based value/mainstream desktops

31. 5.2 Desktop chipsets (4) P4
FSB
SDRAM
Max. 2/4 GB 4
VGA 1
MCH
SDRAM
interface
PC 133, DDR 200/266/333/400, DDR2 400/533
unbuffered, ECC opt. 3
AGP 4X/8X/PCI Express x.16 2
(845/845xx/848P/865xx/
SDRAM
875P/915xx)
SDRAM 3
interface
HI 1.5/DMI
ICH2
ICH4
ICH5(R) 5
ICH6(R) 6
ICH2
ICH4
ICH5(R) 5
ICH6(R) 6
6x v2.2
6x v2.2
6x v2.3
7x v2.3
PCI
ATA/100 2 2 2 1
PCI-X
SATA 2 5 4 6 4
PCI Express x1
ICH
LAN 10/100
4x v1.1
6x v2.0
8x v2.0
8x v2.0
USB
GPI0
v2.1
v2.3
v2.3
v2.3
AC/97
LPC
HDAI
ICH2/4/5/5R /6/6R 5 6
845
845xx
848P
915xx
845
845xx
848P
915xx
FWH
865xx
865xx
875P
875P
BIOS 1
The chipsets including the letter G in their designation provide an integrated graphics controller. 2
The chipsets including the letters GL or GV in their designation don't have an AGP or PCI Express x16 interface. 3
The 865xx, 865 and 915xx chipsets have a dual channel memory link.. 4
The 845 has a max. memory of 3 GB for SDR SDRAMs. 5
The ICH5R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation. 6
The ICH6R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation.
Figure 5.4: The evolution of chipsets intended primarily for P4-based value/mainstream desktops

32. 5.2 Desktop chipsets (3)
Figure 5.5: Main features of Intel’s I/O Control Hubs (ICH) used in P4-based chipsets

33. 5.2 Desktop chipsets (1)
Cores
11/00
1/02
11/02
2/04
Prescott F
8/04
Willamette
Northwood-A
Northwood-B
Prescott
8/01
5/02
5/03
6/04
Willamette
Northwood-B
Northwood-C
Prescott
FSB
400 MHz
400 MHz
400 MHz
533 MHz
533 MHz
800 MHz
800 MHz
800 MHz
800 MHz HT HT HT HT HT HT
EM64T
EM64T
Socket
PGA 423 m
PGA 478 m
PGA 478 m
PGA 478 m
PGA 478 m
PGA 478 m
PGA 478 m
LGA 775
LGA 775
8/03
Chipsets
848P
10/02
5/03
9/03
5/03
845GV/GE/PE
865G/GV/PE
9/01
845
5/03
865P
11/01
5/02
845
845 G/E/GL
4/03
875P
6/04
9/03
6/04
915G/GV/P
Figure 5.6: Intel’s chipsets designed for P4-based value and desktop PCs

34. Northwood-128/ Northwood-B with HT
5.2 Desktop chipsets (5)
Features
845xx family
MCH/GMCH
(Brookdale)
Memory
Single channel SDR/DDR SDRAM
(unbuffered)
Max. memory
2 GB 1
FSB
400 MHz
533/400 MHz
HT support
HT not supported
HT supported 2
DRAM speed
PC133
DDR 266/200
PC133,
PC133,
DDR 266/200
DDR 266/200
DDR 266/200
DDR 266/200
DDR 333/266
DDR 333/266
9/01
11/01
1/02
5/02
5/02
5/02
10/02
10/02
10/02
845
845
845GL
845G
845E
845GV
845GE
845PE
Memory protection
ECC (opt.)
ECC (opt.)
ECC (opt.)
Integrated graphics (IG) IG IG IG IG
Graphics interface up to
AGP 4X
AGP 4X
AGP 4X
AGP 4X
AGP 4X
AGP 8X
ICH
ICH2:
ICH2:
ICH4:
ICH4:
ICH4:
ICH4:
ICH4:
ICH4:
ATA up to
Ultra ATA/100
PCI
PCI 2.2
LAN
10/100 Mbit/s
USB
USB 1.1
USB 1.1
USB 2.0
USB 2.0
USB 2.0
USB 2.0
USB 2.0
USB 2.0
AC '97
AC '97 2.1
AC '97 2.1
AC '97 2.3
AC '97 2.3
AC '97 2.3
AC '97 2.3
AC '97 2.3
AC '97 2.3
Target line at introduction P4 P4
Celeron/P4 P4 P4
Celeron/P4 P4 P4
Target core at introduction
Willamette
Northwood-A
Willamette-128/
Northwood-A
Northwood-B
with HT
Northwood-128/ Northwood-B with HT
Northwood-B with HT
0.18m
0.13m
0.18m
0.13m m
PGA 478 m
PGA 478 m
PGA 478 m
PGA 478 1
The 845 has a max. memory of 2 GB for DDR SDRAMs and 3 GB for SDR SDRAMs. 2
At introduction of the 845G and 845E chipsets (5/02) Intel did not made any notice about supporting hyperthreading. But in 10/02 Intel revealed that the enhanced 845G (B stepping) and the original
845E do support hyperthreading with upgraded BIOSs.
Figure 5.7: Main features of Intel’s 845xx family of chipsets

35. The chipsets 845GL/GV don't offer an AGP interface.
5.2 Desktop chipsets (6) P4
Northwood
FSB
400/533 MHz
VGA 1
845xx
1,2
Max. 2 GB
SDRAM
DDR 200/266/333
SDRAM
interface
(G)MCH
unbuffered, no ECC
AGP 4x 3
HI 1.5
LAN 10/100
MbE
MbE c.
PCI v.2.2
GbE
GbE c.
Ultra ATA/100
(2 ports)
PCI v.2.2
ICH4
(3-6 slots)
GPIO
USB 2.0
(4-6 ports)
AC'97 v.2.3
Audio
CODEC
LPC
FWH
SIO FD KB MS SP PP 1
The chipsets including the letter G in their designation provide an integrated VGA controller. 2
Mainboards based on the 845 chipset have a different configuration since they work with the ICH2. 3
The chipsets 845GL/GV don't offer an AGP interface.
Figure 5.8: Typical configuration of a value/desktop motherboard based on Intel’s 845xx family of chipsets

36. 5.2 Desktop chipsets (1)
Cores
11/00
1/02
11/02
2/04
Prescott F
8/04
Willamette
Northwood-A
Northwood-B
Prescott
8/01
5/02
5/03
6/04
Willamette
Northwood-B
Northwood-C
Prescott
FSB
400 MHz
400 MHz
400 MHz
533 MHz
533 MHz
800 MHz
800 MHz
800 MHz
800 MHz HT HT HT HT HT HT
EM64T
EM64T
Socket
PGA 423 m
PGA 478 m
PGA 478 m
PGA 478 m
PGA 478 m
PGA 478 m
PGA 478 m
LGA 775
LGA 775
8/03
Chipsets
848P
10/02
5/03
9/03
5/03
845GV/GE/PE
865G/GV/PE
9/01
5/03
845
865P
5/02
11/01
845 G/E/GL
4/03
845
875P
6/04
9/03
6/04
915G/GV/P
Figure 5.9: Intel’s chipsets designed for P4-based value and desktop PCs

37. 5.2 Desktop chipsets (7)
Features
915xx family
MCH/GMCH
(Grantsdale)
HT support
HT supported
Memory
Dual channel DDR2/DDR SDRAM
(unbuffered, no ECC)
Max. memory
4 GB 1
FSB
533 MHz
800/533 MHz
DRAM speed
DDR 400/333
DDR2 533/400, DDR 400/333
9/04
6/04
9/04
6/04
910GL 4
915G
915GV
915P
(Grantsdale-GL)
(Grantsdale-G)
(Grantsdale-V)
(Grantsdale-P)
Integrated graphics (IG) IG IG IG
Graphics interface up to
PCI Express x16
PCI Express x16
ICH
ICH6:
IDE up to
Ultra ATA/100
SATA
SATA 1.0a
PCI Express
PCI Express x1 1.0a 2
PCI
PCI 2.3
LAN
10/100 Mbit/s
AC '97 3
AC '97 2.3
HDAI 3
HDAI supported
Target line at introduction
Celeron
Celeron /P4
Target core at introduction
Celeron D
Celeron D/Prescott without EM64T
0.09 m
0.09 m m
PGA 478/LGA 775
LGA 775 1
The max. memory of the 910GL is restricted only to 2 GB. 2
A GbE controller can be attached via the PCI Express x1 link providing 10/100/1000 Mbit/s speeds (e.g. Intel's 82571EB dual channel
GbE controller). 3
The Intel High Definition Audio Interface (HDAI) shares pins with the AC '97 link, so these interfaces cannot be operated concurrently. 4
Supports processors also in socket PGA 478. m
Figures 5.10: Main features of Intel’s 915xx family of chipsets

38. The 915GL/GV chipsets don't offer a PCI Express x16 interface.
5.2 Desktop chipsets (8) P4
Prescott
FSB
533/800 MHz 1
PCI E. x16
VGA
SDRAM
SDRAM
915xx 1
interface
Max. 4 GB
DDR 333/400, DDR2 400/533
(G)MCH
unbuffered, no ECC
SDRAM
PCI E. x16 2
SDRAM
interface
DMI
LAN 10/100
MbE
MbE c.
PCI v.2.3
PCI v.2.3
Ultra ATA/100
(2-4 slots)
(1 port)
PCI E. x1
GbE
GbE c.
SATA
ICH6
(4 ports)
PCI E. x1
(1-2 ports)
GPIO
USB 2.0
(8 ports)
Audio
CODEC
AC'97 v.2.3
LPC
FWH
SIO FD KB MS SP PP 1
The chipsets including the letter G in their designation provide an integrated VGA controller. 2
The 915GL/GV chipsets don't offer a PCI Express x16 interface.
Figure 5.11: Typical configuration of a value/desktop motherboard based on Intel’s 915xx family of chipsets

39. 5.3 Overview of DP server and workstation chipsets
5/01
2/02
11/02
7/03
6/04
Cores
Foster
Prestonia-A
Prestonia-B
Prestonia-C
Nocona
FSB
400 MHz
400 MHz
533 MHz
533 MHz
800 MHz HT HT HT HT HT
EM64T
EM64T
Socket
PGA 603 m
PGA 603 m
PGA 603 m
PGA 603 m m
PGA 604
Chipsets
8/04
DP-servers
2/02
11/02
E7320
E7500
E7501
8/04
E7520
DP-workstations
5/01
860
6/04
11/02
E7525
E7505
Figure 5.12: Intel’s chipsets designed for P4-based DP-servers and workstations

40. 5.4 DP server chipsets (1)
5/01
Features
860
E75xx/E73xx family
MCH
HT support
HT supported
Nr. of mem. channels
Dual channel
Dual channel SDRAM
Memory
RDRAM
(registered, ECC)
Max. memory
4 GB
16 GB 1
Memory protection
ECC (opt.)
FSB
400 MHz
400 MHz
533 MHz
800 MHz
EM64T support
EM64T supported
DRAM speed
PC 800/600
DDR 200
DDR 266 /200
DDR 333/266
DDR 333
DDR2 400
DDR2 400
2/02
11/02
11/02
8/04
8/04
6/04
E7500
E7501
E7505 1
E7320
E7520 2
E7525
(Plumas)
(Placer)
(Lindenhurst-VS)
(Lindenhurst)
(Tumwater)
Aim
DP WS
DP server
DP server
DP WS
DP server
DP server
DP WS
Graphics interface up to
AGP 4X
AGP 8X
PCI Express x16
Additional high speed if.
2x HI
3x HI 2.0
3x HI 2.0
1x HI 2.0
1x PCI Express x8
3x PCI Express x8
1x PCI Express x8
RAS/RASUM
RASUM 4
RASUM 4
RAS 4
RASUM 4
RASUM 4
RASUM 4
ICH
ICH2:
ICH3-S:
ICH3-S:
ICH4: 4
ICH5R:/6300ESB: 3
ICH5R:/6300ESB: 3
ICH5R:/6300ESB: 3 4
IDE up to
Ultra ATA/100
Ultra ATA/100
Ultra ATA/100
Ultra ATA/100
Ultra ATA/100
Ultra ATA/100
Ultra ATA/100
SATA
SATA 1.0a
SATA 1.0a
SATA 1.0a
PCI
PCI 2.2
PCI 2.2
PCI 2.2
PCI 2.2
PCI 2.3/PCI 2.2
PCI 2.3/PCI 2.2
PCI 2.3/PCI 2.2
PCI-X
/PCI-X 2.2
/PCI-X 2.2
/PCI-X 2.2
PCI Express x1
USB
USB 1.1
USB 1.1
USB 1.1
USB 2.0
USB 2.0
USB 2.0
USB 2.0
LAN
10/100 Mbit/s
10/100 Mbit/s
10/100 Mbit/s
10/100 Mbit/s
10/100 Mbit/s
10/100 Mbit/s
10/100 Mbit/s
AC' 97
AC '97 2.1
AC '97 2.2
AC '97 2.2
AC '97 2.3
AC '97 2.2/AC '97 2.3
AC '97 2.2/AC '97 2.3
AC '97 2.2/AC '97 2.3
Target cores at introduction
Foster
Prestonia-A
Prestonia-B
Nocona
Technology/Socket
0.18m/m
PGA 603
0.13m/m
PGA 603
0.09m/m
PGA 604 1
The 7505 supports also unbuffered DDR SDRAMs. 2
The 7520 includes an integrated four channel DMA engine in contrast to the E7320. 3
The ICH5R incorporates a RAID controller (Redundant Arrays of Indepentdent Disks) that utilizes the dual SATA ports for a high-performance RAID Level 0 configuration. 4
Reliability, Availability, Serviceability, Usability, Manageability
Figure 5.13: The evolution of Intel’s chipsets designed for P4 Xeon-based dual processor (DP) servers and workstations (WS)

41. 5.4 DP server chipsets (2) P4 P4
Xeon
Xeon
FSB
HI 2.0/PCI E. x8
MCH 1
SDRAM
SDRAM
Max GB
interface
DDR 200/266/333/400, DDR2 400
High speed if.
HI 2.0/PCI E. x8
with RASUM 2
registered, ECC
SDRAM
SDRAM
HI 2.0/PCI E. x8
(E7500/7501/7320 /7520) 3
interface
HI 1.5
ICH3-S
ICH5R 5
6300ESB 6
ICH3-S
ICH5R 5
6300ESB 6
6x v2.2
6x v2.3
4x v2.2
PCI
ATA/100 2 2 2
4x v.2.2
PCI-X
SATA 2 5 2 6
PCI Express x1
ICH
LAN 10/100
6x v1.1
8x v2.0
4x v2.0
USB
GPI0 5
v2.2
v2.3
v2.2
AC' 97
(ICH3-S/5R /6300ESB)
LPC
HDAI
E7500
E7520
E3520
E7500
E7520
E7320
FWH
E7501
E7501
BIOS 1
The 16-bit HI 2.0 link is used to add PCI/PCI-X bridges (6700PXH), while the PCI Express x8 links are usually configured as two independent x4 ports,
each providing the possibility to add a PCI/PCI-X brigde (e.g. 6700PXH) or a dual GbE controller 2
Reliability, Availability, Serviceability, Usability, Manageability 3
The E7320 has only a single PCI Express x8 high speed interface 4
An external SATA controller is needed only in connection with the ICH3-S 5
The ICH5R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation
The 6300ESB SATA supports soft RAID. 6
Figure 5.14: The evolution of DP-server chipsets of P4 cores

42. 5.4 DP server chipsets (3) P4 P4
Prestonia
Prestonia
PCI-X v.2.2
FSB
400/533 MHz
(1-2 slots)
HI 2.0
E7500/E7501
SDRAM
GbE
GbE c.
SDRAM
8/12/16 GB
PCI-X
HI 2.0
interface
MCH
bridge
DDR 200/266
SATA
SATA c.
registered, ECC opt.
SDRAM
HI 2.0
(with RASUM)
SDRAM
interface
SCSI
SCSI c.
HI 1.5
PCI-X v.2.2
(1-2 slots)
SVGA
Video c.
PCI v.2.2
MbE
MbE c.
Ultra ATA/100
(2 ports)
PCI v.2.2
ICH3-S
(3 slots)
GPIO
USB v. 1.1
(5 ports)
LPC
FWH
SIO FD KB MS SP PP
Figure 5.15: Typical configuration of a DP-server motherboard based on Intel’s E7500/E7501 chipsets

43. 5.4 DP server chipsets (4) P4 P4
Nocona
Nocona
FSB
800 MHz
PCI-X v.1.0b
(1 slot)
PCI E. x8
SDRAM
GbE
E7520
SDRAM
GbE c.
interface
16/24/32 GB
PCI-X
PCI E. x8
MCH
bridge
DDR 266/333, DDR2 400
SCSI
SCSI c.
SDRAM
registered, ECC opt.
PCI E. x8
PCI E. x8
SDRAM
(with RASUM)
interface
PCI-X v.1.0b
(or 2x x4)
(1-2 slot)
HI 1.5
PCI v.2.3
SVGA
Video c.
Ultra ATA/100
(2 ports)
PCI v.2.3
(0-1 slot)
ICH5R
SATA
(2 ports)
USB v. 2.0
(4 ports)
GPIO
AC' 97 v.2.3
LPC
FWH
SIO FD KB MS SP PP
Figure 5.16: Typical configuration of a DP-server motherboard based on Intel’s E7520 chipset (including the ICH5R)

44. 5.5 DP workstation chipsets (1)
Xeon
Xeon
FSB
MCH 1
SDRAM
SDRAM
Max. 16 GB
AGP 4X/8X/PCI E. x16
interface
DDR 200/266/333, DDR2 400
with RASUM 2
registered, ECC opt.
SCSI SATA GbE
SDRAM
PCI-X
HI 2.0, PCI E x8
SDRAM
bridge
( /E7505/7525)
2,3
interface
HI 1.5
ICH2
ICH4
ICH5R 4
6300ESB 5 4
ICH2
ICH4
ICH5R
6300ESB 5
6x v2.2
6x v2.2
6x v2.3
4x v2.2
PCI
ATA 2 2 2 2
4x v.2.2
PCI-X
SATA 2 4 2 5
ICH
PCI Express x1
LAN 10/100
4x v1.1
6x v2.0
8x v2.0
4x v2.0
USB
(ICH2/4/5R/6300ESB)
GPI0
v2.1
v2.3
v2.3
v2.2
AC' 97
LPC
HDAI
860
E7505
E7525
E7525
860
E7505
E7525
E7525
FWH
BIOS 1
Reliability, Availability, Serviceability, Usability, Manageability 2
The first chipsets of this line (the 860) worked with DRDRAMs while using PC 600/800. 3
The MCH of the 860 provides two 16-bit high speed interfaces, to add PCI v2.2 bridges (P64H). 4
The ICH5R includes an integrated RAID controller that utilizes the dual SATA ports for a high performance RAID Level 0 implementation 5
The 6300ESB SATA supports soft RAID.
Figure 5.17: The evolution of DP-workstation chipsets of P4 cores

45. 5.5 DP workstation chipsets (2)
Prestonia B/C
Prestonia B/C
PCI-X v.2.2
(1-2 slots)
FSB
533 MHz
GbE
GbE c.
PCI-X
HI 2.0
E7505
SDRAM
bridge
SDRAM
8/12 GB
SATA
SATA c.
interface
MCH
DDR 200/266
AGP 8x
SDRAM
registered, ECC opt.
SCSI
SCSI c.
(with RASUM)
SDRAM
interface
PCI-X v.2.2
(1-2 slots)
HI 1.5
PCI v.2.2
MbE
MbE c.
Ultra ATA/100
PCI v.2.2
(2 ports)
(1-2 slots)
ICH4
USB 2.0
(4 ports)
GPIO
AC'97 v.2.2
Audio
CODEC
LPC
FWH
SIO FD KB MS SP PP
Figure 5.18: Typical configuration of a DP-workstation motherboard based on Intel’s E7505 chipset

46. 5.5 DP workstation chipsets (3)
Nocona
Nocona
FSB
800 MHz
PCI E. x16
E7525
SDRAM
SDRAM
interface
16/24/32 GB x4
MCH
DDR 266/330
PCI E. x8
SDRAM
registered, ECC opt.
PCI-X
PCI-X x4
(with RASUM)
SDRAM
GbE c.
GbE c.
interface
bridge
HI 1.5
PCI-X v.2.2
GbE
GbE c.
PCI v.2.2
Ultra ATA/100
(1-2 slots)
ICH
(2 ports)
PCI-X v.2.2
(2 slots)
SATA
6300ESB
(2 ports)
USB 2.0
(4 ports)
GPIO
AC'97 v.2.2
Audio
CODEC
LPC
FWH
SIO FD KB MS SP PP
Figure 5.19: Typical configuration of a DP-workstation motherboard based on Intel’s E7525 chipset

47. 6. Bandwidth considerations

48. 6. Bandwidth considerations (1)
Peak aggregate bandwidth
FSB
64-bit
8 * f Mbyte/s
FSB
SDRAM-interface
64-bit
8 * f Mbyte/s
SDRAM
Figure 6.1: Main features of the FSB and SDRAM interfaces

49. 6. Bandwidth considerations (2)
Figure 6.2: Main features of MCH/ICH interfaces used in Intel’s P4-based chipsets

50. 6. Bandwidth considerations (3)
Figure 6.3: Main features of high speed MCH interfaces of Intel’s P4-based chipsets

51. 6. Bandwidth considerations (4)
ICH5
FWH
SDRAM
interface
DDR 266/333/400
unbuffered, no ECC
Ultra ATA/100
Audio
GPIO
FSB 400/533/800 MHz
LPC
HI 1.5 P4
Northwood B/C
865xx
4 GB
MbE c.
PCI v.2.3
CSA (HI 1.5)
MbE
SIO FD KB MS SP PP
(3 slots)
GbE c.
GbE
USB 2.0
(6-8 ports)
CODEC
AC'97 v.2.3
SATA
(2 ports)
AGP 8x
VGA
(GMCH) 1
2132
266
2132-
3200
133
1.4
2*100
2*150 ~5
Figure 6.4: Peak bandwidth values (Mbyte/s) in typical desktops, based on Intel’s 865xx chipsets

52. 6. Bandwidth considerations (5)P4
Prescott
FSB
533/800 MHz
PCI E. x16
SDRAM
4 GB
PCI E. x16
8000
2664- 1
SDRAM
915xx
4264
interface
DDR 333/400, DDR2 400/533
(G)MCH
unbuffered, no ECC
PCI E. x16
2664-
SDRAM
VGA
8000
4264
SDRAM
interface
DMI
2000
PCI v.2.3
MbE
MbE c.
133
PCI v.2.3
Ultra ATA/100
(2-4 slots)
1*100
(1 ports)
PCI E. x1
GbE
GbE c.
500
ICH6
SATA
PCI E. x1
4*150
(4 ports)
(1-2 ports)
500
USB 2.0
GPIO 60
(8 ports)
Audio
CODEC
AC'97 v.2.3
1.4 ~5
LPC
FWH
SIO FD KB MS SP PP
Figure 6.5: Peak bandwidth values (Mbyte/s) in typical desktops, based on Intel’s 915xx chipsets

53. 6. Bandwidth considerations (6)P4 P4
Prestonia
Prestonia
PCI-X v.2.2
FSB
400/533 MHz
(1-2 slots)
HI 2.0
1066
1600-
2128
SDRAM
8/12/16 GB
GbE
E7500/E7501
GbE c.
SDRAM
PCI-X
HI 2.0
interface
DDR 200/266
bridge
1066
MCH
SATA
SATA c.
registered, ECC opt.
1600-
2128
SDRAM
HI 2.0
SDRAM
1066
interface
SCSI
SCSI c.
(with RASUM)
PCI-X v.2.2
HI 1.5
266
(1-2 slots)
PCI v.2.2
SVGA
Video c.
133
LAN
MbE
Ultra ATA/100
MbE c.
2*100
(2 ports)
PCI v.2.2
ICH3-S
(3 slots)
GPIO
USB v. 1.1
1.5
(5 ports) ~5
LPC
FWH
SIO FD KB MS SP PP
Figure 6.6: Peak bandwidth values (Mbyte/s) in typical DP-servers, based on Intel’s E7500/E7501 chipsets

54. 6. Bandwidth considerations (7)P4 P4
Nocona
Nocona
FSB
800 MHz
3200
PCI-X v.1.0b
PCI E. x8
4000
16/24/32 GB
GbE
2128-
3200
SDRAM
GbE c.
E7520
SDRAM
PCI-X
PCI E. x8
interface
DDR 266/333, DDR2 400
bridge
4000
MCH
registered, ECC opt.
SCSI
SCSI c.
2128-
3200
SDRAM
SDRAM
PCI E. x8
4000
interface
PCI-X v.1.0b
(with RASUM)
PCI E. x8
(or 2x x4)
HI 1.5
266
PCI v.2.3
SVGA
Video c.
133
Ultra ATA/100
2*100
(2 ports)
LAN
MbE
MbE c.
SATA
PCI v.2.3
ICH5R
2*150
(2 ports)
USB v. 2.0 60
(4 ports)
GPIO
AC' 97 v.2.3
~1.4 ~5
LPC
FWH
SIO FD KB MS SP PP
Figure 6.7: Peak bandwidth values (Mbyte/s) in typical DP-servers, based on Intel’s E7520/ICH5R chipset

55. 6. Bandwidth considerations (8)P4 P4
Prestonia B/C
Prestonia B/C
PCI-X v.2.2
(1-2 slots)
FSB
533 MHz
4264
GbE
GbE c.
PCI-X
HI 2.0
SDRAM
bridge
1066
E7505
1600-
SDRAM
8/12 GB
SATA
SATA c.
MCH
2132
interface
DDR 200/266
AGP 8x
registered, ECC opt.
SDRAM
SCSI
SCSI c.
2132
1600-
SDRAM
2132
interface
(with RASUM)
PCI-X v.2.2
(1-2 slots)
HI 1.5
266
PCI v.2.2
GbE
GbE c.
133
2*100
Ultra ATA/100
(2 ports)
PCI v.2.2
ICH4
USB 2.0 60
(4 ports)
GPIO
AC'97 v.2.2
Audio
CODEC
1.4 ~5
LPC
FWH
SIO FD KB MS SP PP
Figure 6.8: Peak bandwidth values (Mbyte/s) in typical DP-workstations, based on the Intel’s E7505 chipset

56. 6. Bandwidth considerations (9)P4 P4
Nocona
Nocona
FSB
800 MHz
PCI E. x16
E7525
2132-
SDRAM
16/24/32 GB
8000
SDRAM
2664
interface
DDR 266/333
MCH
PCI E. x8
registered, ECC opt.
4000
2132-
SDRAM
SDRAM
2664
interface
(with RASUM)
HI 1.5
266
PCI-X v.2.2
GbE
GbE c.
133
PCI v.2.2
2*100
Ultra ATA/100
PCI-X v.2.2
533
(2 ports)
6300ESB
SATA
USB 2.0 60
2*150
(2 ports)
(4 ports)
ICH
GPIO
Audio
CODEC
AC'97 v.2.2
1.4 ~5
LPC
FWH
SIO FD KB MS SP PP
Figure 6.9: Peak bandwidth values (Mbyte/s) in typical DP-workstations based on the Intel’s E7525 chipset

57. 7. Special aspects of the implementation

58. 7. Special aspects of the implementation
7.1 Attaching the display
7.2 PCI-X bridges
7.3 Attaching MbE/GbE controllers
7.4 Attaching SCSI controllers
7.5 Implementation of ICHs

59. 7.1 Attaching the display
Typical use: P4
MCH
ICH
VGA
Value/mainstream desktops
with the letter G in their
designation (e.g. 845G/GL/GV)
Entry level servers based on
the E7221 P4
MCH
ICH
PCI
32 bit/33 MHz
video c.
VGA
(mostly ATI Rage XL)
Entry level servers based on the E7210
DP-servers
On-board P4
Off-board
MCH
ICH
AGP 4x/8x/
PCI E. x8/x16
video c.
VGA
Value/mainstream desktops
excluding those with the letters
GL or GV in their designation
High end desktops/entry level
workstations
DP-workstations
(e.g. 845GL/GV)
Figure 7.1: Alternatives for attaching a display in P4-based motherboards

60. Figure 7.2: Use of PCI-X bridges to attach dedicated controllers
SATA c.
GbE c.
SATA
GbE
SCSI c.
SCSI
bridge
HI/HI2.0/PCI E.
Figure 7.2: Use of PCI-X bridges to attach dedicated controllers

61. 7.2 PCI-X bridges (2)
P64H 16 HI
PCI
32/64-bit
33/66 MHz 64
(82806AA)
P64H2
HI 2.0
PCI 2.2/PCI-X 1.0
(82870P2)
PXH-V
1/4/8
PCI E. 1.0a x1/x4/x8
(6702PXH)
PXH
(6700PXH)
PCI E. 1.0a x4/x8
PCI 2.3/PCI-X 1.0b 1
4/8
Used in e.g. 860
E7500/7501/7505
E7221
E7320/7520/7525 2
The interface can be independently configured as either a PCI bus or a PCI-X bus running at 33/66
or 66/100/133 MHz resp.
The bridge can operate either in x4 or x8 mode.
Figure 7.3: PCI-X bridges used in Intel’s P4-based motherboards

62. 7.3 Attaching MbE/GbE controllers (1)P4 P4 P4
MCH
MCH
HI 1.5
HI 1.5
LAN 10/100 1
PCI
MbE c.
ICH
MbE c.
ICH
Examples
82562ET
845xx (opt.
82550PM
E7500/7501/7505 2
or standard)
82562EZ
848P 3
82551QM
E7500/7501 2
865xx 3
E7210
875P 3
915xx 4
Value/mainstream desktops
Early DP servers/workstations
(Furthermore E7210) 1
The LAN 10/100 interface is also designated as the LCI interface (LAN Connect Interface). 2
The 82550PM or the 8255IQM is available in DP servers and workstations usually in addition to a GbE c.
As an exception some early E7500 based motherboards provide only one or two MbE controllers. 3
Most of the enlisted motherboards provide either a MbE controller attached to the LAN 10/100 interface
or a GbE controller attached to the CSA interface. 4
A few 915xx based Intel motherboards provide either a 82562EZ MbE controller or the Marvell 88E8050
PCI Express x1-based GbE controller.
Figure 7.4: Alternatives used to attach a MbE controller in Intel’s P4-based motherboards

63. 7.3 Attaching MbE/GbE controllers (2)P4 P4 P4 P4 P4 P4
GbE c.
CSA
PCI-X
HI 2.0
MCH
GbE
MCH
GbE
GbE c.
PCI-X
brigde
MCH
MCH
HI 1.5
HI 1.5
HI 1.5
HI 1.5
PCI
GbE
GbE c.
ICH
ICH
ICH
PCI-X
ICH
GbE
GbE c.
(6300ESB)
Examples
82540EM
845xx
82547EI
848P 4 1
82545EM 2
E7501
E7500/7501/7505 5
82541GI
E7320/7525 (w/6300ESB)
865xx 4
E7205
875P 4
82546EB (D)
82541PI
E7320/7525 (w/6300ESB) 3
82541GI
875P
E7500/7501/7505
915xx
82547GI
875P
925X
E7210
82541GB
E7320/7525 (w/6300ESB) 3
E7210
82541PI
E7221
E7520(w/ICH5R)
All categories
Mainstream desktops
Early DP servers/workstations
Advanced DP servers/workstations
(Furthermore the E7210) 1
Ususally in companion with a MbE controller such as the 82550PM or the 82551QM. 2
The 82541GI is used either in 32-bit/33MHz or 32-bit/66 MHz mode. 3
The 82541PI and the 8254GB is used in the 32-bit/33 MHz mode. 4
Most of the enlisted motherboards provide either a MbE controller attached to the LAN 10/100 interface or a GbE controller attached to the CSA interface. 5
Ususally in companion with a MbE controller such as the 82551QM.
Figure 7.5: Widely used alternatives to attach a GbE controller in Intel’s P4-based motherboards via legacy buses

64. 7.3 Attaching MbE/GbE controllers (3)P4 P4 P4 P4 P4
GbE c.
PCI-X
PCI-X x4
GbE
GbE c. x4
GbE
bridge
PCI E. x8
PCI E. x8
MCH x4
MCH x4
MCH
DMI
HI 1.5
HI 1.5
GbE c.
PCI E. x1
GbE c.
ICH
ICH
ICH
GbE c.
(ICH6/
(ICH5/
ICH6R)
(ICH5R)
6300ESB)
Examples
82570EI 1
915GV
82546GB (D)
E7520/E7525 (w/ICH5R)
82571EB
E7320
(88E8050 ) 2
925X
E7520
(BCM5721 ) 3
E7221
E7525
Advanced single processor motherboards
Advanced DP servers/workstations
Advanced DP servers/workstations 1
Used to date (2/05) in Commel's FS-979 motherboards. 2
From Marvell 3
From Broadcom
Figure 7.6: Alternatives used to attach a GbE controller inIntel’s P4-based motherboards via the PCI Express bus

65. 7.4 Attaching SCSI controllersP4 P4 P4 P4 P4 P4
FSB
PCI E. x8
FSB
HI 2.0
PCI E. x8
FSB
PCI-X
MCH x8
MCH
MCH
SCSI c.
bridge
SCSI c.
PCI-X
PCI-X
(E7500/7501)
bridge
(E7320)
SCSI c.
bridge
(E7520)
PCI-X
(P64H2)
PCI-X
(PXH-V)
PCI-X
(PXH)
ICH
ICH
ICH
Typical use:
Adaptec A W
LSI Logic 53C1020
Adaptec AIC-7902
(Ultra 160, dual channel)
(Ultra 320, single channel)
(Ultra 320, dual channel)
Adaptec AIC-7901
LSI Logic 53C1030
(Ultra 320, single channel)
(Ultra 320, dual channel)
Adaptec AIC-7902
(Ultra 320, dual channel)
Early DP-servers
Advanced mid-range DP-servers
Advanced high-end DP-servers
Figure 7.7: Alternatives used to attach a SCSI controller in Intel’s P4-based motherboards Remark: A few entry-level servers and DP-workstations incorporate also a SCSI controller, like some based on the E7221 or E7505 chipsets

66. 7.5 Implementation of ICHs (1)
to (G)MCH
HI 1.5
8-bit/66 MHz*4
Multiplexer
PCI Bus 0
PCI Bus 1
32-bit/33 MHz
32-bit/33 MHz
USB 2.0
D:29, F0
D:8, F0
(2 ports)
USB UHCI c. #1
LAN 10/100
LAN 10/100
USB 2.0
D:29, F1
(2 ports)
USB UHCI c. #2
USB 2.0
D:29, F2
(2 ports)
USB UHCI c. #3
D:29, F7
USB 2.0 EHCI c.
PCI
D:30, F0
(6 master)
HUB/PCI bridge
ICH4
D:31, F0
LPC
LPC bridge
ATA
D:31, F1
(2 port)
ATA c.
SMBus
D:31, F3
SMBus
D:31, F5
AC'97 Audio c.
AC'97 v. 2.3
D:31, F6
AC'97 0 Modem c.
D: Device
F: Function
UHCI: Universal Host Controller Interface
EHCI: Enhanced Host Controller Interface
Figure 7.8: Simplified structure of the ICH4

67. 7.5 Implementation of ICHs (2)
to (G)MCH
DMI
4*1-bit/2.5 GHz
Multiplexer
PCI Bus 0
PCI Bus 1
32-bit/33 MHz
32-bit/33 MHz
IHDA/AC'97 v.2.3
D27, F0
D8, F0
IHDA/AC'97 c.
LAN 10/100
LAN 10/100
PCI E. X1 v1.0a
D28, F0
PCI E. port 1
PCI E. x1 v1.0a
D28, F1
PCI E. port 2
PCI E. x1 v1.0a
D28, F2
PCI E. port 3
PCI E. x1. v1.0a
D28, F3
PCI E. port 4
USB 2.0
D29, F0
(2 ports)
USB UHCI c.
USB 2.0
(2 ports)
D29, F1
USB UHCI c.
USB 2.0
(2 ports)
D29, F2
USB UHCI c.
USB 2.0
D29, F3
(2 ports)
USB UHCI c.
D29, F7
USB 2.0 EHCI c.
ICH6
PCI v.2.3
D30, F0
PCI to PCI bridge
D30, F2
AC'97 Audio c.
AC'97/IHDA
D30, F3
AC'97 Modem c.
LPC
D31, F0
LPC c.
ATA
D31, F1
(1 port)
ATA c.
SATA
D31, F2
(4 port)
SATA c.
SMBus
D31, F3
SMBus c.
D: Device
F: Function
UHCI: Universal Host Controller Interface
EHCI: Enhanced Host Controller Interface
Figure 7.9: Simplified structure of the ICH6