1. Combinatorial Logic Design Practices
ECGR2181
These are all different interpretations of the same bit string.
Reading: Chapter 6
Logic System Design I

2. Documentation Standards
Requirements
Block diagrams
first step in hierarchical design
Schematic diagrams
HDL programs (ABEL, Verilog, VHDL)
Timing diagrams
Circuit descriptions
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3. Block Diagram
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4. Flat schematic structure
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5. Hierarchichal schematic structure
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6. Other Documentation Timing diagrams Circuit descriptions
Output from simulator
Specialized timing-diagram drawing tools
Circuit descriptions
Text (word processing)
Can be as big as a book
Typically incorporate other elements (block diagrams, timing diagrams, etc.)
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7. Signal names and active levels
Signal names are chosen to be descriptive.
Active levels -- HIGH or LOW
named condition or action occurs in either the HIGH or the LOW state, according to the active-level designation in the name.
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8. Example HIGH when error occurs Logic Circuit ERROR OK_L Logic Circuit
LOW when error occurs
ERROR_L
ERROR
ERROR1_L
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9. Logic System Design I

10. Timing diagram with propagation delay
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11. Logic System Design I

12. Example - Requirements
You must first identify the requirements of a device before you can design it. Using the requirements to create a timing diagram helps to ensure the requirements are understood.
Req. 1: The circuit will have four inputs: A[7:0], B[7:0], choose, valid.
Req. 2: The circuit will have two outputs: outbus[7:0] and out_valid.
Req. 3: When valid=0, outbus and out_valid will be all zeros.
Req. 4: When valid=1, out_valid=1, the value of A will be routed to outbus if choose=0, otherwise B will be routed to outbus.
Req. 5: After valid goes from 0 to 1, outbus and out_valid will change anywhere from 2 to 4ns later.
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13. Example – Timing Diagram
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14. Programmable Logic Arrays (PLAs)
Any combinational logic function can be realized as a sum of products.
Idea: Build a large AND-OR array with lots of inputs and product terms, and programmable connections.
n inputs
AND gates have 2n inputs -- true and complement of each variable.
m outputs, driven by large OR gates
Each AND gate is programmably connected to each output’s OR gate.
p AND gates (p<<2n)
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15. Example: 4x3 PLA, 6 product terms
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16. Programmable Array Logic (PALs)
How beneficial is product sharing?
Not enough to justify the extra AND array
PALs ==> fixed OR array
Each AND gate is permanently connected to a certain OR gate.
Example: PAL16L8
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17. 8 outputs, with 7 ANDs per output 1 AND for 3-state enable
10 primary inputs
8 outputs, with 7 ANDs per output
1 AND for 3-state enable
6 outputs available as inputs
more inputs, at expense of outputs
two-pass logic, helper terms
Note inversion on outputs
output is complement of sum-of-products
newer PALs have selectable inversion
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18. Designing with PALs
Compare number of inputs and outputs of the problem with available resources in the PAL.
Write equations for each output using HDL.
Compile the HDL program, determine whether minimized equations fit in the available AND terms.
If no fit, try modifying equations.
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19. Decoders General decoder structure Typically n inputs, 2n outputs
2-to-4, 3-to-8, 4-to-16, etc.
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20. Binary 2-to-4 decoder Note “x” (don’t care) notation.
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21. 2-to-4-decoder logic diagram
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22. Example: 2-to-4 decoder Architecture
positional correspondence with entity definition
built-in library components
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23. Decoder Symbol
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24. MSI 2-to-4 decoder Input buffering (less load) NAND gates (faster)
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25. Complete 74x139 Decoder
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26. 3-to-8 decoder
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27. 74x138 3-to-8-decoder symbol
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28. Dataflow-style program for 3-to-8 decoder
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29. Dataflow-style program for 3-to-8 decoder
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30. Decoder cascading
4-to-16 decoder
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31. More cascading
5-to-32 decoder
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32. Decoder applications Microprocessor memory systems
selecting different banks of memory
Microprocessor input/output systems
selecting different devices
Microprocessor instruction decoding
enabling different functional units
Memory chips
enabling different rows of memory depending on address
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33. Example – Microprocessor Application
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34. Encoders vs. Decoders
Decoder
Encoder
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35. Binary encoders
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36. Need priority in most applications
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37. 8-input priority encoder
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38. Priority-encoder logic equations
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39. 74x148 8-input priority encoder
Active-low I/O
Enable Input
“Got Something”
Enable Output
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40. 74x148 circuit
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41. 74x148 Truth Table
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42. Cascading priority encoders
32-input priority encoder
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43. Multiplexers
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44. Multiplexer - Gate-Level Modeling - Verilog
2-to-1 Multiplexer
// 2-to-1 Multiplexer module
module mux_2 (out, i0, i1, sel); // header
input i0, i1, sel; // input & output ports
output out;
wire x1, x2, x3; // internal nets
or (out, x2, x3); // form output
and (x2, i0, x1); // i0  sel’
and (x3, i1, sel); // i1  sel
not (x1, sel); // invert sel
endmodule
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45. Multiplexer - Dataflow Modeling - Verilog
4-bit Multiplexer
// Four-bit 2-to-1 multiplexer
module mux_4bit (Out, A, B, sel);
input [3:0] A, B;
input sel;
output [3:0] Out;
assign Out = sel ? B, A;
endmodule
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46. Multiplexer - Behavioral Modeling - Verilog
Conditional Statements
module mux4_to_1 (A, B, C, D, OUT, select);
input [7:0] A, B, C, D;
input [1:0] select;
output [7:0] OUT;
reg [7:0] OUT;
(A or B or C or D or select)
case (select)
2’d0: OUT = A;
2’d1: OUT = B;
2’d2: OUT = C;
2’d3: OUT = D;
endcase
end
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47. 74x151 8-input multiplexer
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48. 74x151 truth table
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49. CMOS transmission gates
2-input multiplexer
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50. Other multiplexer varieties
2-input, 4-bit-wide
74x157
4-input, 2-bit-wide
74x153
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51. Barrel shifter design example
n data inputs, n data outputs
Control inputs specify number of positions to rotate or shift data inputs
Example: n = 16
DIN[15:0], DOUT[15:0], S[3:0] (shift amount)
Many possible solutions, all based on multiplexers
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52. 16 16-to-1 muxes 16-to-1 mux = 2 x 74x151 8-to-1 mux + NAND gate
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53. 4 16-bit 2-to-1 muxes 16-bit 2-to-1 mux = 4 x 74x157 4-bit 2-to-1 mux
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54. Properties of different approaches
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55. 2-input XOR gates
Like an OR gate, but excludes the case where both inputs are 1.
XNOR: complement of XOR
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56. XOR and XNOR symbols
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57. Gate-level XOR circuits
No direct realization with just a few transistors.
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58. Equality Comparators 1-bit comparator 4-bit comparator EQ_L
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59. 8-bit Magnitude Comparator
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60. Other conditions
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61. Adders Basic building block is “full adder” Truth table:
1-bit-wide adder, produces sum and carry outputs
Truth table:
X Y Cin S Cout
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62. Full-adder circuit
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63. Ripple adder Speed limited by carry chain
Faster adders eliminate or limit carry chain
2-level AND-OR logic ==> 2n product terms
3 or 4 levels of logic, carry lookahead
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64. 74x283 4-bit adder Uses carry lookahead internally
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65. carry-in from previous stage
“generate”
“half sum”
carry-in from previous stage
“propagate”
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66. Ripple carry between groups
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67. Lookahead carry between groups
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68. Subtraction
Subtraction is the same as addition of the two’s complement.
The two’s complement is the bit-by-bit complement plus 1.
Therefore, X – Y = X + Y + 1 .
Complement Y inputs to adder, set Cin to 1.
For a borrow, set Cin to 0.
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69. Full subtractor = full adder, almost
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70. Multipliers
8x8 multiplier
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71. Full-adder array
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72. Faster carry chain
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