1. QUARTUS II Version 9.1 service pack 2
Gregg Chapman
Spring 2016

2. BACKGOUND The Demystification if Digital Circuitry in 2 Minutes or Less

3. Diodes

4. Transistors

5. Logic Gates

6. R-S Latch and D Flip-Flop

7. Register (Memory)
One 8-bit Memory Address

8. Logic Cell
Look-Up-Table
Combinatorial Logic
Latches

9. Field Programmable Gate Array

10. DE2 – 115 Board

11. DE2 – 115 Board
Cyclone IV E – EP4CE115F29C7
FPGA

12. QUARTUS II Version 9.1 service pack 2
Gregg Chapman
Spring 2016

13. PROJECTS Creating a New Project Archiving a Project
Restoring a Project from Archive
Opening an Existing Project

14. CIRCUITS DESIGN USING SCHEMATICS

15. CIRCUITS DESIGN New Schematic Sheet The MegaWizard Making Connections
Rubber Band Mode
Busses verses Wires
Generate Pins
Creating Blocks
Copying Blocks
Compiling
Programming
What to select if your windows get messed up

16. COMMON OVERSIGHTS AND PROBLEMS

17. Troubleshooting Checksheet
(90% of problems are caused by one or more of the items listed here. Please go through the checklist before raising your hand for help.)
□ Have you chosen the correct FPGA
Cyclone IV E , EP4CE115F29C7
□ Is what you wish to compile at the TOP LEVEL
□ Have you performed ALL 3 STEPS for setting up pin assignments
Copy the .csv file to your Project Folder
Add the .csv file to your Project
Import the .csv pin assignment file to your Project
NOTE: If you only import the pin assignments, they will appear but the compiler won’t use them.

18. Troubleshooting Checksheet
(90% of problems are caused by one or more of the items listed here. Please go through the checklist before raising your hand for help.)
□ Under the Files Tab: Do you show any files that are preceded by ..\
This mean that you have added files OUTSIDE of your Project (The program will behave erratically or not work at all until this is resolved)
□ Did you compile
□ Did you reprogram the board after you compiled

19. Troubleshooting Checksheet
□ Have you chosen the correct FPGA
Cyclone IV E , EP4CE115F29C7
□ Is what you wish to compile at the TOP LEVEL
□ Have you performed ALL 3 STEPS for setting up pin assignments
Copy the .csv file to your Project Folder
Add the .csv file to your Project
Import the .csv pin assignment file to your Project
□ Under the Files Tab: Do you show any files that are preceded by ..\
□ Did you compile
□ Did you reprogram the board after you compiled

20. Other Common Problems Bad Project Locations Anywhere but the Z Drive
My Documents
Projects inside of other Projects
Bad Naming Conventions
Spaces and Apostrophes

21. The Red Error of Death

22. Bad Writes to ROM and Constants

23. Quartus Tools

24. In System Memory Editor
Under Tools pull-down menu In-System Memory Content Editor
In Instance Manager window, select a Constant or Memory Read Data from In System Memory
To write a Constant or Memory, edit the number (changes BLUE) and Write Data (changes RED again if successful).
If memory is changing dynamically. Select the Continuously Read Button

25. Signal Tap II – Clock Set-up
Select Tools pull-down menu  Signal Tap II Logic Analyzer
In Hardware  Setup  Select USB Blaster  Add Hardware  Close
Select a Clock: Signal Configuration  Clock  List (add clock pin if needed, i.e. CLOCK_50)
Set the Sample Depth
Set Filter to Signal Tap II: pre-synthesis
Select List
Add the Clock signal
Under Data, Select a Sample Depth

26. Signal Tap II
Change to the Signal Tap II Analyzer Window by selecting the Data tab.
Right click and select Add Node.
Click List
Highlight signals and add by pressing > button
Clear the checkmarks in Trigger enables (unless otherwise specified)
Recompile the Project
At .stp window -> OK
No triggers -> OK
Enable STP file -> Yes
Wait for Compile to complete
DON’T FORGET TO REPROGRAM FPGA
Run Analysis