1. VLSI Testing Lecture 2: Yield & Quality
Dr. Vishwani D. Agrawal
James J. Danaher Professor of Electrical and Computer Engineering
Auburn University, Alabama 36849, USA
IIT Delhi, Aug 17, 2013, 11:00AM-12:00PM
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

2. Lecture 2 Yield & Quality
Contents
Yield and manufacturing cost
Clustered defect yield formula
Defect level
Test data analysis
Example: SEMATECH chip
Summary
Problems to solve
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

3. VLSI Chip Yield
A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by defects created by the fabrication process.
A chip with no manufacturing defect is called a good chip.
Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y.
Cost of a chip:
Cost of fabricating and testing a wafer
———————————————————————Yield x Number of chip sites on the wafer
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

4. Clustered VLSI Defects
Good chips
Faulty chips
Defects
Wafer
Unclustered defects
Wafer yield = 12/22 = 0.55
Clustered defects (VLSI)
Wafer yield = 17/22 = 0.77
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

5. Lecture 2 Yield & Quality
Yield Parameters
Defect density (d ) = Average number of defects per unit of chip area
Chip area (A)
Clustering parameter (α)
Negative binomial distribution of defects, p (x ) = Prob (number of defects on a chip = x )
G (a+x ) (Ad /a) x
= ─────── . ──────────
x ! G (a) (1+Ad /a) a+x
where Γ is the gamma function
a = 0, p (x ) is a delta function (maximum clustering)
a = ∞ , p (x ) is Poisson distribution (no clustering)
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

6. Lecture 2 Yield & Quality
Yield Equation
Y = Prob ( zero defect on a chip ) = p (0)
Y = ( 1 + Ad / a ) - a
Example: Ad = 1.0, α = 0.5, Y = 0.58
Y = e – Ad
Unclustered defects: α = ∞,
Example: Ad = 1.0, α = ∞, Y = 0.37
too pessimistic !
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

7. Defect Level or Reject Ratio
Defect level (DL) is the ratio of faulty chips among the chips that pass tests.
DL is measured as parts per million (ppm).
DL is a measure of the effectiveness of tests.
DL is a quantitative measure of the manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable.
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

8. Lecture 2 Yield & Quality
Determination of DL
From field return data: Chips failing in the field are returned to the manufacturer. The number of returned chips normalized to one million chips shipped is the DL.
From test data: Fault coverage of tests and chip fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL.
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

9. Modified Yield Equation
Three parameters:
Fault density, f = average number of stuck-at faults per unit chip area
Fault clustering parameter, β
Stuck-at fault coverage, T
The modified yield equation:
Y (T ) = (1 + TAf / b) – b
Assuming that tests with 100% fault coverage
(T = 1.0) remove all faulty chips,
Y = Y (1) = (1 + Af / b) – b
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

10. Lecture 2 Yield & Quality
Defect Level
Y (T ) – Y (1)
DL (T ) = ———————
Y (T )
( b + TAf ) b
= 1 – ——————
( b + Af ) b
Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A, β is the fault clustering parameter. Af and β are determined by test data analysis.
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

11. Example: SEMATECH Chip
Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont
116,000 equivalent (2-input NAND) gates
304-pin package, 249 I/O
Clock: 40MHz, some parts 50MHz
0.8m CMOS, 3.3V, 9.4mm x 8.8mm area
Full scan, 99.79% fault coverage
Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock
Data obtained courtesy of Phil Nigh (IBM)
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

12. Test Coverage from Fault Simulator
Stuck-at fault coverage, T
Vector number
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

13. Lecture 2 Yield & Quality
Measured Chip Fallout
Measured chip fallout, 1 – Y (T )
Vector number
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

14. Stuck-at fault coverage, T
Model Fitting
Chip fallout vs. fault coverage
Y (1) =
Chip fallout and computed 1 – Y (T )
Measured chip fallout
Y (T ) for Af = 2.1 and b = 0.083
Stuck-at fault coverage, T
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

15. Lecture 2 Yield & Quality
Computed DL
237,700 ppm (Y = 76.23%)
Defect level in ppm
Stuck-at fault coverage (%)
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

16. Lecture 2 Yield & Quality
Summary
VLSI yield depends on two process parameters, defect density (d ) and clustering parameter (α).
Yield drops as chip area increases; low yield means high cost.
Fault coverage measures the test quality.
Defect level (DL) or reject ratio is a measure of chip quality.
DL can be determined by an analysis of test data.
For high quality: DL << 500 ppm, fault coverage ~ 99%
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

17. Lecture 2 Yield & Quality
Two Problems to Solve
Using the expression for defect level on Slide 10, derive test coverage (T ) as a function of fault clustering parameter (β), defect level (DL), and average number of faults (Af ) on a chip.
Find the defect level for:
Fault density, f = 1.45 faults/sq. cm
Fault clustering parameter, β = 0.11
Chip area = 1 cm2
Fault Coverage, T = 95%
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

18. DL = 1 – [(β + TAf )/(β + Af )]β (1 – DL)1/β = (β + TAf )/(β + Af )
Solution to Problem 1
Defect level, DL, is given on Slide 10, as follows:
DL = 1 – [(β + TAf )/(β + Af )]β
where T is the fault coverage, Af is the average number of faults on a chip of area A, and β is a fault clustering parameter. Further manipulation of this equation leads to the following result:
(1 – DL)1/β = (β + TAf )/(β + Af )
or T = [{(β + Af )(1 – DL)1/β – β}/(Af )] × 100 percent
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality

19. Solution to Problem 2 Defect level, DL, as given on Slide 10, is:
DL(T ) = 1 – [(β + TAf )/(β + Af )]β
Substituting,
Fault density, f = 1.45 faults/sq. cm
Fault clustering parameter, β = 0.11
Chip area = 1 cm2
Fault Coverage, T = 95%
We get,
DL(T ) = or 5,220 parts per million
Copyright 2001, Agrawal & Bushnell
Lecture 2 Yield & Quality