1. Interconnect Dominated Design and Analysis
Chung-Kuan Cheng
CSE Department
UC San Diego

2. Research Scope Packaging architecture
Replace current backplane, board, substrates
SPICE_Diego + Thermal, Mechanical Simulation
Heart Beat Aids

3. Research Results
Architecture Designs, Hardware Systems, Software Packages
Quality of Patents
Technical Books
Journal Papers, Conference Papers

4. Research Process
Why
What
Where
How

5. Research Subjects Scalable System: Power, Delay, Cost, Reliability
A Analysis: Spice, Power, Clock, Variations (STA)
B BioEng: EKG, Signal Network
C Interconnect Networks: Packaging, Interconnect, Networks
D Data path: Adders, Shifters, CMDL

6. A Analysis Spice: Parallel Computing, Operator Splitting Power Clock
Analysis in t and s domains, Natural Frequency (G+jwC)-1
Synthesis of networks and decap.
Clock
Analysis and synthesis of mesh and tree
Variations: Stochastic Process, Monte Carlo
Altera, Fastrack, Fujitsu, Qualcomm, Synopsys
Rui, Vincent, Ling, Wanping, Renshen

7. B BioEng EKG: Probe, Measurement, Algorithm Signal Networks
Yi, Wanping

8. C Interconnect Networks
Packaging
3D Floorplanning, Pin Breakaway, Signal Integrity
Interconnect
Passive Wire Technologies
Networks
Hierarchy, Topology, Performance
ADS, HFSS, EIP, PowerSpice, Sigrity
Yuanfang, Haikun, Yi, Renshen

9. D Data Paths Shifters Adders: Ling’s adder, High Radix
Differential Circuit Style
Haikun, Yi, Ling, Renshen

10. Process Research as the highest priority (Call me anytime)
Follow-up and go through the exploration (Don’t drop the ball)
Plan ahead (Schedule, Proactive)
Utilize the team (Establish Personal Networks)

11. Group Presentation Statement of the problem Previous Schedule
Progress Report
Weekly and Monthly Schedule

12. Presentations Main theme of the talk Key point of each page Practice
Audio tape recording
Questions and Answers
Problems behind the questions