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CPRE 583 Reconfigurable Computing

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1 CPRE 583 Reconfigurable Computing
Lecture 4: 9/03/2010 (VHDL Overview 2 ) Instructor: Dr. Phillip Jones Reconfigurable Computing Laboratory Iowa State University Ames, Iowa, USA

2 Overview Mini Literary Survey VHDL review 2

3 Literary Survey Start with searching for papers from on IEEE Xplorer: Advanced Search (Full Text & Meta data) Find popular cross references for each area For each area try to identify 1 good survey papers For each area Identify 2-3 core Problems/issues For each problem identify 2-3 Approaches for addressing For each approach identify 1-2 papers that Implement the approach.

4 Literary Survey: Example Structure
Hardware Accelerated Bioinformatics P1 P2 P3 A1 A2 A3 A1 A2 A1 A2 I1 I1 I2 I1 I1 I1 I1 I2 I1 5-10 page write up on your survey tree

5 Literature Survey: Bioinformatics
Date: 6/11/2010 Name : Pooja Mhapsekar

6 Categories: Bioinformatics
Sequence alignment Sequence Secondary Structure Secondary Structure assembly Prediction design

7 Types of Sequence Alignment
Sequence Alignment pairwise structural multiple

8 Types of Sequence Alignment
pairwise structural multiple short non- short read read HMM LCS heuristic method DP frequency vector DP- Dynamic Programming HMM- Hidden Markov Model LCS- Longest Common Subsequence

9 Types of Sequence Alignment
pairwise structural multiple short non- short read read spaced-seed Borrow-wheeler transform Spaced-seed Suffix array and SHRiMP Zoom Smith- Waterman BWA Bowtie Maq SHRiMP Segemehl e.g. RazerS, RMAP, BWT, Cloudburst, 2BWT.

10 Types of Sequence Alignment
pairwise structural multiple Protein RNA DALI TOPOFIT Combinatorial extension SSAP FOLDALIGN GANGSTA MAMMOTH RAPIDO SABERTOOTH

11 Types of Sequence Alignment
Structural Pairwise Multiple DP Simulated Annealing Progressive Iterative method construction Genetic algorithm Hidden Markov Models DP –Dynamic Programming

12 Techniques for MSA and the software for each technique
Multiple DP Simulated Annealing Carllo-Lipman MSA MSASA Progressive Iterative method construction DIALIGN PPRN/PPRP MUSCLE CLUSTALW Genetic algorithm Hidden Markov PSALIGN Models T-Coffee RNA Proteins SAM RAGA SAGA POA HMMER

13 Secondary Structure Prediction
Secondary Structure Prediction (Sequence types) Nucleotide secondary structure Protein structure prediction prediction

14 Nucleotide Secondary Structure Prediction
(Sequence types) Nucleotide secondary structure Protein structure prediction prediction Single sequence Comparitive Structure prediction SSP lowest suboptimal energy free structures Structure Dynamic m-fold programming Nussoniv Zuker

15 Nucleotide Secondary Structure Prediction- Approaches for comparative SSP
(Sequence types) Nucleotide secondary structure Protein structure prediction prediction Single sequence Comparative Structure prediction SSP Align then Align and Fold then fold fold align

16 Secondary Structure Prediction
(Sequence types) Nucleotide secondary structure Protein structure prediction prediction Secondary Tertiary Structure Structure Chou-Fasman Machine GOR learning

17 Secondary Structure Prediction
(Sequence types) Nucleotide secondary structure Protein structure prediction prediction Secondary Tertiary Structure Structure Ab initio Structural protein classes modelling prediction Comparative Protein Side Chain modelling geometry homology protein modelling threading

18 Secondary Structure Design(SSD)
Secondary Structure Design (Sequence types) Nucleic acid secondary Protein structure design structure design

19 Secondary Structure Design(SSD) – Approaches for nucleic acid design
(Sequence types) Nucleic acid secondary Protein structure design structure design Heuristic Geometric methods models Thermodynamic Sequence models Symmetry minimization

20 Secondary Structure Design(SSD) – Approaches for nucleic acid design
(Sequence types) Nucleic acid secondary Protein structure design structure design Heuristic Geometric methods models Thermodynamic models rnaDesign INFO-rna RNA-SSD RNAinverse

21 Secondary Structure Design(SSD) – Approaches for nucleic acid design
(Sequence types) Nucleic acid secondary Protein structure design structure design Heuristic Geometric methods models(tertiary structure) Thermodynamic models   GIDEON UNIQUIMER 3D Tiamat  Nanoengineer

22 Secondary Structure Design(SSD)
(Sequence types) Nucleic acid secondary Protein structure design structure design computer ancestral models reconstruction protein genetic energetics (MFE) algorithm e.g. IPRO, Abalone, EGAD, RosettaDesign, SHARPEN, WHAT IF Source:

23 Sequence assembly Sequence assembly: It refers to aligning and merging fragments of a much longer DNA sequence in order to reconstruct the original sequence. Sequence assembly Genome assemblers EST assemblers (transcribed mRNA) Protein assembly

24 Sequence assembly Sequence assembly: It refers to aligning and merging fragments of a much longer DNA sequence in order to reconstruct the original sequence. Sequence assembly Genome assemblers EST assemblers (transcribed mRNA) Protein assembly Greedy Approach hierarchical sequencing Overlap-layout Alignment-layout- Consensus consensus prefix tree based Eulerian path/De Bruijn graph

25 Sequence assembly Sequence assembly: It refers to aligning and merging fragments of a much longer DNA sequence in order to reconstruct the original sequence. Sequence assembly Genome assemblers EST assemblers (transcribed mRNA) Protein assembly Knowledge-based approach

26 Sequence assembly Sequence assembly: It refers to aligning and merging fragments of a much longer DNA sequence in order to reconstruct the original sequence. Sequence assembly Genome assemblers EST assemblers (transcribed mRNA) Protein assembly miraEST Newbler

27 VHDL: IF and CASE constructs
IF THEN ELSE can be mapped to a 2:1 Multiplexer (Mux) sel = b“0” IF (sel = ‘0’) THEN out_1 <= in_0; ELSE out_1 <= in_1 END IF; x”C” 4 2:1 Mux in_0 4 out_1 x”C” 4 x”D” in_1

28 VHDL: IF and CASE constructs
Mapping a CASE statement to a 4:1 Mux CASE sel is WHEN “00” => out_1 <= in_0; WHEN “01” => out_1 <= in_1; WHEN “10” => out_1 <= in_2; WHEN “11” => out_1 <= in_3 WHEN OTHERS => END CASE; sel = b“10” 2 x”C” 4 in_0 4:1 Mux 4 x”D” in_1 4 out_1 x”7” 4 x”7” in_2 4 x”2” in_3 Why do we need others here?

29 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic

30 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic IP src

31 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic IP dest IP src

32 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic src port IP dest IP src

33 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic dest port src port IP dest IP src

34 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic length dest port src port IP dest IP src

35 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Data 1 length dest port src port IP dest IP src

36 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Data 2 Data 1 length dest port src port IP dest IP src

37 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Data 3 Data 2 Data 1 length dest port src port IP dest

38 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Send Alert Data 3 Data 2 Data 1 length dest port src port IP dest

39 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Send Alert r o C length dest port src port IP dest

40 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Send Alert n r o C length dest port src port

41 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Send Alert ! n r o C length dest port

42 Streaming Network application (MP2)
Detect patterns in payload (e.g. “Corn!”) Place the number of detections in last byte of payload FSM + Management logic Send Alert Modify Packet ! n r o C length dest port

43 Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload Draw out logic, and data flow!!! Alert FSM Alert Register & Counter Management Packet Length output sel position corn_cnt Packet Input Process 2:1 Mux Packet Output Process

44 Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload Alert FSM Alert Register & Counter Management Packet Length output sel position corn_cnt Packet Input Process 2:1 Mux Packet Output Process

45 Alert FSM Design Alert signal when the pattern “corn!” is detected
Z = {Alert} “c”/0 “o”/0 “r”/0 “n”/0 c o r n ! others/0 Start others/0 others/0 others/0 “!”/1

46 Alert FSM Design Alert signal when the pattern “corn!” is detected
Output Packet’s Length Z = {Alert,length_vld,pack_length} X = {vld,input} : Note “?” is don’t care “c”/0 “o”/0 “r”/0 “n”/0 c o r n ! others/0 Start others/0 others/0 others/0 “!”/1

47 Alert FSM Design Alert signal when the pattern “corn!” is detected
Output Packet’s Length Z = {Alert,length_vld,pack_length} X = {vld,input} : Note “?” is don’t care UDP ports 1,“c”/0,0,0 1,“o”/0,0,0 1,“r”/0,0,0 1,“n”/0,0,0 1,”?”/0,0,0 1,”?”/0,0,0 c o r n ! IPH_5 UDP length 1,others/0,0,0 1,”?”/0,1,length IPH_2 1,others/0,0,0 1,others/0,0,0 1,”?”/0,0,0 1,others/0,0,0 Start IP 1,“!”/1,0,0 Start

48 Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload Alert FSM Alert Register & Counter Management Packet Length output sel position corn_cnt Packet Input Process 2:1 Mux Packet Output Process

49 Register & Counter Manager
Register & Counter Components Design of Manager

50 Register and Counter Components
reset load sel(reset,load) set_value 3:1 Mux 8 reg_val 8 DFF Counter reset load inc sel(reset,load,inc) set_value 4:1 Mux count 8 8 + 8 inc_val DFF

51 Practice: Write VHDL(process for each)
Register Name : process(clk) begin if(clk’event and clk=‘1’) then logic here end if; end process Name reset load sel(reset,load) 3:1 Mux reg_val set_value 8 8 DFF CASE sel is WHEN “00” | “11”=> out_1 <= in_0; WHEN “01” => out_1 <= in_1; WHEN OTHERS => END CASE; Counter reset load inc sel(reset,load,inc) set_value 4:1 Mux count 8 8 + 8 inc_val DFF

52 Register VHDL Name : process(clk) begin if(clk’event and clk=‘1’) then
CASE reset&load is WHEN “10” | “11” => reg_val <= 0; WHEN “01” => reg_val <= set_value; WHEN OTHERS => reg_val <= reg_val; END CASE; end if; end process Name Register reset load sel(reset,load) set_value 3:1 Mux 8 reg_val 8 DFF

53 Register VHDL Name : process(clk) begin if(clk’event and clk=‘1’) then
CASE sel is WHEN “10” | “11” => reg_val <= 0; WHEN “01” => reg_val <= set_value; WHEN OTHERS => reg_val <= reg_val; END CASE; end if; end process Name sel <= reset&load; Register reset load sel(reset,load) set_value 3:1 Mux 8 reg_val 8 DFF

54 Counter VHDL + Name : process(clk) begin
if(clk’event and clk=‘1’) then CASE reset&load&inc is WHEN “100” | “101” | “110”| “111” => count <= 0; WHEN “010” | “011” => count <= set_value; WHEN “001” => count <= count + inc_val; WHEN OTHERS => count <= count; END CASE; end if; end process Name Counter reset load inc sel(reset,load,inc) set_value 4:1 Mux inc_val count 8 8 + 8 DFF

55 Counter VHDL + Name : process(clk) begin
if(clk’event and clk=‘1’) then CASE sel is WHEN “100” | “101” | “110”| “111” => count <= 0; WHEN “010” | “011” => count <= set_value; WHEN “001” => count <= count + inc_val; WHEN OTHERS => count <= count; END CASE; end if; end process Name sel <= reset&load&inc; Counter reset load inc sel(reset,load,inc) set_value 4:1 Mux inc_val count 8 8 + 8 DFF

56 Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt Packet Input Process 2:1 Mux Packet Output Process

57 Register and Counter Manger
Alert inc corn_cnt Counter inc_val 1 load set_value reset reset inc position Valid_data Counter inc_val 1 load set_value reset reset length_vld load Register Packet_Length_reg Packet_Length set_value

58 Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt Packet Input Process 2:1 Mux Packet Output Process

59 Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt Packet Input Process 2:1 Mux Packet Output Process

60 Output sel Comparator outputs 1 if inputs match Packet_length
Position sel corn_cnt 1 2:1 Mux Data_to_output Data_from_input

61 Output sel: VHDL NOT in a process!
Data_to_output <= corn_cnt when (Packet_length = Position) else Data_from_input Comparator outputs 1 if inputs match Packet_length Comparator Position sel corn_cnt 1 2:1 Mux Data_to_output Data_from_input

62 Architecture Detect patterns in payload (e.g. “Corn!”)
Place the number of detections in last byte of payload Alert Alert FSM Register & Counter Management Packet Length reset length_vld reset position output sel Packet_length data data_vld corn_cnt Packet Input Process 2:1 Mux Packet Output Process

63 Modify corn! counter for Multiple matches
Alert inc Counter corn_cnt inc_val 1 load set_value reset reset

64 Modify corn! counter for Multiple matches
Alt_0 Alt_1 inc Alt_2 Counter Alt_3 corn_cnt inc_val 1 load set_value reset reset

65 Modify corn! counter for Multiple matches
Alt_0 Alt_1 OR inc Alt_2 Counter Alt_3 corn_cnt inc_val 1 load set_value reset reset

66 Modify corn! counter for Multiple characters
Alt_0 Alt_1 OR inc Alt_2 Counter Alt_3 sel(Alt0,Alt1, Alt2,Alt3) corn_cnt 1 inc_val 4:1 Mux 2 load 3 4 set_value reset reset NOT in a process! Alt_merge <= Alt0 & Alt1 & Alt2 & Alt3; inc_val <= 4 when (Alt_merge = “1111”) 3 when (Alt_merge = “0111” or Alt_merge = “1011” ...) 2 when (Alt_merge = “0011” or Alt_merge = “0110” ...) else 0

67 Modify corn! counter for Multiple matches
Alt_0 Alt_1 OR inc Alt_2 Counter Alt_3 corn_cnt inc_val 1 load set_value reset reset

68 State Machine design next Friday

69 Questions/Comments/Concerns

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