1. North America 3DS-IC Committee (Three-dimensional Stacked Integrated Circuits)
Liaison Report
April 2011

2. Outline Leadership Organization Chart Meeting Information
Task Force Updates
April 2011
NA 3DS-IC Committee

3. Leadership Committee Co-chairs Chris Moore (Semilab)
Sesh Ramaswami (Applied Materials)
Urmi Ray (Qualcomm)
Andy Rudack (SEMATECH)
New!
April 2011
NA 3DS-IC Committee

4. Organization Chart NA 3DS-IC Committee Wafer Bonded Stacks TF
C: Urmi Ray (Qualcomm)
C: Andy Rudack (SEMATECH)
C: Chris Moore (Semilab) C: Sesh Ramaswami (Applied Materials)
Wafer Bonded Stacks TF
L: Andy Rudack (SEMATECH)
Inspection & Metrology TF
L: Chris Moore (Semilab)
Thin Wafer Handling TF
L: Urmi Ray (Qualcomm)
April 2011
NA 3DS-IC Committee

5. Meeting Information Last meeting Next meeting
March 29 for NA Spring 2011 Meetings San Jose, California
Next meeting
July 12 for SEMICON West 2011 Meetings San Francisco, California
April 2011
NA 3DS-IC Committee

6. NA 3DS-IC Committee Kick-off Meeting Held Jan 12 via teleconference/web meeting
Attendance
37 participants
Companies represented include:
Amkor, Applied Materials, ASE, Brooks Automation, Corning, DISCO, eda 2 asic, Entegris, eSilicon, EVG, ITRI, KLA-Tencor, Lasertec, Miraial, Nitto Denko, Olympus, Qualcomm, SEMATECH, Semilab, Sharp, SUMCO, TI
Discussed formation of three (3) proposed task forces
Wafer Bonded Stacks TF
Inspection & Metrology TF
Thin Wafer Handling TF
April 2011
NA 3DS-IC Committee

7. Task Force Overview 3DS-IC Wafer Bonded Stacks TF
Approved late January 2011
Charter:
The BWS Task Force will actively create and/or modify specifications that reflect bonded wafer stacks parameters and the wafer bonding process.
Scope:
Identify new wafer parameters that reflect adequate ranges for bonded wafer stacks
Modify/create document to reflect adequate ranges for bonded wafer stacks
Identify other SEMI standards that are adversely affected by BWS parameters
Update referenced standards: create/modify standards to reflect BWS parameters
April 2011
NA 3DS-IC Committee

8. Task Force Overview 3DS-IC Inspection & Metrology TF
Approved late January 2011
Charter:
Develop standards for metrology and inspection methods to be used in measuring the properties of TSV’s, bonded wafer stacks, and dies used in the 3DS-IC manufacturing process.
Scope:
Examples of needed standards include (but are not limited to):
TSV physical properties (i.e., depth, top, bottom CD, side wall, etc.)
Bonded wafer stack properties (i.e., overlay, bond inspection)
Defect metrology
Dies
April 2011
NA 3DS-IC Committee

9. Task Force Overview 3DS-IC Thin Wafer Handling TF
Approved late January 2011
Charter:
Develop standards for reliable handling and shipping of thin wafers, dies (e.g., Micro-pillar Grid array -MPGA) used in 3DS-IC high-volume manufacturing (HVM)
Define thin wafer handling requirements including physical interfaces used in 3DS-IC manufacturing
Define shipping requirements, including packaging, reliability, and other relevant criteria. This will also include MPGA ship/handle requirements
April 2011
NA 3DS-IC Committee

10. Task Force Overview 3DS-IC Thin Wafer Handling TF (cont’d) Scope:
Formulate a common set of requirements and prioritize critical areas for standardization, resulting in a short-list of required standards (inspection, shipping etc) in the topics listed below. Other topics may be added based on additional inputs
Thin wafer and Die Shipping related activities:
Examples: Shipping carriers for thin wafer (wafer cassette, box or frame), Shipping carrier for dies (MPGA), Reliability Test methods
Transportation vibration testing
Drop-shock
Other – new tests?
Thin wafer handling-related activities:
Examples: Process and Metrology Tools and Test methods
Whole wafer inspection for damage (crack, break etc)Macro level
Damage to features – microbump, pad etc micro level
Universal carrier concept
Automation
April 2011
NA 3DS-IC Committee

11. New SNARFs [1/3]
Doc – New Standard: Specification for Parameters for Bonded Wafer Stacks
Rationale
Current wafer standards (SEMI M1) do not adequately address the needs of wafers used in bonded wafer stacks. Wafer thickness, edge bevel, notch, mass, bow/warp and diameters are changed when wafer stacks are bonded together, or wafer stacks bonded and thinned. These deviations from wafer parameters specified in SEMI M1 have numerous impacts in other equipment and hardware standards that reference SEMI M1, and drives a new standard to reflect wafer parameters associated with bonded and bonded/thinned wafer stacks.
Scope
Develop a standard that will meet the needs of bonded wafer stacks using temporary bonding to carrier wafers. This standard will reflect the new parameters (including thickness, edge bevel, notch, mass, bow/warp and diameters, etc.) associated with bonded wafer stacks including bonded and thinned stacks.
This standard will include both Silicon and glass carrier wafers.
Task Force
Bonded Wafer Stacks TF
April 2011
NA 3DS-IC Committee

12. New SNARFs [2/3]
Doc – New Standard: Specification for Identification and Marking for Bonded Wafer Stacks
Rationale
Current wafer identification standards and wafer marking standards do not adequately address the needs of bonded wafer stacks. Location (e.g. backside near notch for SEMI T7) will be removed during backside thinning operations or edge-trim operations, or buried under an opaque layer of silicon and rendered un-readable by optical readers when bonded. Multiple wafer stacks will combine wafers with multiple process history, including tracking of temporary carrier wafers, and a standard needs to be developed to combine and track bonded wafer stacks with multiple wafer histories.
Scope
Develop an identification standard that will meet the needs of bonded wafer stacks. The initial focus will be temporary bonding and permanent bonding as driven by contributions.
Task Force
Bonded Wafer Stacks TF
April 2011
NA 3DS-IC Committee

13. New SNARFs [3/3]
Doc – New Standard: Guide for Multi-Wafer Transport and Storage Containers for Thin Wafers
Rationale
Current standards for wafer transport and storage containers (shipping boxes, FOUP, FOSBs) do not adequately address the reliable storage and transportation of thin wafers and dice on tape frame used in 3DS-IC manufacturing. Wafer thicknesses of um will need significant changes to the current design criteria of current wafer transport and storage containers. This will address robust handling and shipping of thin wafers, including changes in securing the wafers. New inspection processes will be addressed in the Inspection and Metrology TF.
Scope
Develop a thin wafer handling and shipping guide that will meet the needs of 3DS-IC manufacturing.
Include:
Standards for tape frame
Standards for thin wafer on tape frame
Requirements of capacity of containers
Transportation/vibration and mechanical shock requirements
Task Force
Thin Wafer Handling TF
April 2011
NA 3DS-IC Committee

14. 3DS-IC at NA Standards Spring 2011 Meetings March 29
A new task force will be chartered to develop standard(s) for dimensions and sizes for carrier wafers as well as edge trimming of the device wafer
The output of this task force will be used in the development of the bonded wafer stacks specification by the Bonded Wafer Stacks TF
TFOF and associated SNARF(s) are currently being drafted
Bonded Wafer Stacks TF
Members were tasked to submit standardization proposals for consideration. Currently, there are currently 47 items on the “wish list”
2 SNARFs approved by the committee
(Doc. 5173) New Standard: Specification for Parameters for Bonded Wafer Stacks
(Doc. 5174) New Standard: Specification for Identification and Marking for Bonded Wafer Stacks
SNARF in development
Specification for transport and storage containers for bonded wafer stacks
April 2011
NA 3DS-IC Committee

15. 3DS-IC at NA Standards Spring 2011 Meetings March 29
Inspection & Metrology TF
TF will develop and distribute a process flow map with known, as well as potential, areas for metrology identified. Members are asked to report which of these areas they can contribute
IMEC presentation on “Metrology for Bonding”
SNARF drafted for 3DS-IC TSV Physical Parameters
Rationale
A number of different technologies exist which can be used to measure various physical parameters of a TSV or arrays of TSV’s such as pitch, top CD, top area, depth, taper (or sidewall angle), bottom area, bottom CD
However at this time it is difficult to try to compare and/or correlate results from the various technologies for the various ranges of TSV dimensions. In some cases parameter are called by similar names but are different aspects of the same measurement
This standard would attempt to group the various technologies results in such a way that correlations and comparisons are valid or in cases where they are not clearly indicate this
SNARF will be finalized and submitted for approval
April 2011
NA 3DS-IC Committee

16. 3DS-IC at NA Standards Spring 2011 Meetings March 29
Thin Wafer Handling TF
New SNARF approved by the committee
(Doc. 5175) New Standard: Guide for Multi-Wafer Transport and Storage Containers for Thin Wafers
Reviewed standard on tape frame (SEMI G74)
April 2011
NA 3DS-IC Committee

17. NA 3DS-IC West 2011 Meeting Schedule [DRAFT]
North America Standards Meetings at SEMICON West 2011 (July 11-14)
San Francisco Marriott Marquis Hotel (across from Moscone Convention Center)
55 Fourth Street, San Francisco, California 94103
Tuesday, July 12
Inspection & Metrology Task Force (8:00 AM to 10:00 AM)
Wafer Bonded Stacks Task Force (10:00 AM to 12:00 Noon)
Thin Wafer Handling Task Force (1:00 PM to 3:00 PM)
NA 3DS-IC Committee (3:00 PM to 5:00 PM)
The schedule above is subject to change. The committee is considering parallel TF meetings (vs sequential) at SEMICON West.
For more information, please visit:
For more information about SEMICON West 2011, please visit:
April 2011
NA 3DS-IC Committee

18. Thank You!
For more information or participate in any NA 3DS-IC activities, please contact Paul Trio at SEMI
April 2011
NA 3DS-IC Committee

19. Participating Companies
Albany Nanotech
AllVia
Altera
AMD
Amkor
ANjAY Technology
Applied Materials
ASE
Attoscopy
BroadPak
Brooks Automation
CEA/LETI
Corning
DAETEC
DISCO
Dynaloy
eda2asic
Entegris
Epistar
ESI
EVG
Fraunhofer
GlobalFoundries
IBM
IMEC
Intel
ITRI
KLA-Tencor
Lasertec
Maxim
Metryx
Miraial
MoSys
Neocera
Nikon
NIST
Novellus
Olympus-ITA
PEER Group
Planarity
Qualcomm
Raytex
Rudolph Technologies
Samsung
Sematech
Semilab
SigmaTech
Soitec
SUSS
Tamar Technology
TechSearch TerePac
Tessera
Texas Instruments
Tezzaron
TOK America
TSMC
WaferMasters
Xilinx
Zygo
April 2011
NA 3DS-IC Committee

20. SEMI Staff Contacts
James Amano Director, SEMI International Standards +1 (408) 943 – 7977
Paul Trio Sr. Manager, North America Standards Operations +1 (408) 943 – 7041
April 2011
NA 3DS-IC Committee

21. Back-up
April 2011
NA 3DS-IC Committee

22. Task Force Updates 3DS-IC Wafer Bonded Stacks TF (cont’d)
First meeting held February 23
Presentation on 3D lessons learned
Discussion on 3D standards gap associated with bonded wafer pairs
Members tasked to submit standardization proposals for consideration
Target SNARF (Standards New Activity Report Form) submission at NA Spring 2011 meetings
April 2011
NA 3DS-IC Committee

23. Task Force Updates 3DS-IC Inspection & Metrology TF (cont’d)
First meeting held March 9
Reviewed TF charter and scope
Physical TSV
Depth, size, aspect ratio
Design rules and how they impact properties of copper
TSV reveal
Handoff requirements
Backside properties
Inspection
Wafer bonding
Need to clarify on
Warp, defects, bows
Planes, reference system
Measuring methodology
April 2011
NA 3DS-IC Committee

24. Task Force Updates 3DS-IC Thin Wafer Handling TF (cont’d)
First meeting held February 16
Companies represented: Amkor, ASE, Brooks, Corning, Elpida, Intel, SEMATECH, SUSS, TOK
Reviewed and finalized TF charter and scope
Discussed which existing SEMI Standards can be leveraged for wafer spec and handling
April 2011
NA 3DS-IC Committee