1. Computer Architecture
Processor Design

2. Chapter Outline The Design Process
A 1-Bus Microarchitecture for the SRC
Data Path Implementation
Logic Design for the 1-Bus SRC
The Control Unit
The 2- and 3-Bus Processor Designs
The Machine Reset
Machine Exceptions
15 November 2018
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3. The Design Process
Focus from RTN machine description to computer system design:
Design of the central processing unit
Logic designer’s point of view
RTN and logic design tools presented in Chapter 2 will be used extensively.
Goal is not simply to present a design of SRC but also to do the design in the way a designer would approach it.
15 November 2018
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4. The Design Process
In Chapter 2, the informal description of SRC was formalized by means of an RTN description.
Some of the machine hardware was also specified:
Programmer-visible registers.
Next steps:
Specification of the data path.
The set of interconnections and auxiliary registers needed to accomplish the overall changes an instruction makes in the programmer-visible objects.
RTN useful in describing the actions that take place in the data path.
Assumptions about how hardware components behave in describing the data path. This set of assumptions becomes a specification for the logic design of the data path hardware.
Hardware design based on specifications.
Control signals must be contemplated that must be generated to cause actions to take place.
Strobes to load registers
Gates to apply outputs to a bus.
Control Unit design
Generates the control signals in correct order to effect the correct data path activity.
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5. Abstract and Concrete Register Transfer Descriptions
The abstract RTN for SRC in Chapter 2 defines “what,” not “how”
A concrete RTN uses a specific set of real registers and buses to accomplish the effect of an abstract RTN statement
Same abstract RTNs that implement the same ISA could have different concrete RTNs.
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6. Fig 4.1 Block Diagram of 1-Bus SRCá 3 1 . ñ 2 D P i n G r a W t R I M T o m e y s u b h F g 4 , l p B - /
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7. Fig 4.2 High-Level View of the 1-Bus SRC DesignA L U C á 3 1 . ñ 2 R I M T o m e r y s u b t D P B - i g n a l p
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8. Constraints Imposed by the Microarchitecture
One bus connecting most registers allows many different RTs, but only one at a time
Memory address must be copied into MA by CPU
Memory data written from or read into MD
First ALU operand always in A, result goes to C
Second ALU operand always comes from bus
Information only goes into IR and MA from bus
A decoder (not shown) interprets contents of IR
MA supplies address to memory, not to CPU bus A L U C á 3 1 . ñ 2 R I M T o m e r y s u b t D P B - i g n a l p
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9. Abstract and Concrete RTN for SRC: add Instruction
Abstract RTN:
(IR ← M[PC]: PC ← PC + 4; instruction_execution);
instruction_execution := ( • • •
add (:= op= 12) → R[ra] ← R[rb] + R[rc]:
Tbl 4.1 Concrete RTN for the add Instruction 3 1 á 3 1 . . ñ R
Step RTN
T0 MA ¬ PC: C ¬ PC + 4;
T1 MD ¬ M[MA]: PC ¬ C;
T2 IR ¬ MD;
T3 A ¬ R[rb];
T4 C ¬ A + R[rc];
T5 R[ra] ¬ C; 3 2 3 2 - b i t 3 2 3 1 g e n e r a l P C p u r p o s e r e g i s t e r s R 3 1 IF
IEx. I R A M A A B T o m e m o r y s u b s y s t e m A L U C M D
Parts of 2 RTs (IR ¬ M[PC]: PC ¬ PC + 4;) done in T0
Single add RT takes 3 concrete RTs (T3, T4, T5) C
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10. Concrete RTN Gives Information About Sub-units
The ALU must be able to add two 32-bit values
ALU must also be able to increment B input by 4
Memory read must use address from MA and return data to MD
Two RTs separated by “:” in the concrete RTN, as in T0 and T1, are operations at the same clock
Steps T0, T1, and T2 constitute instruction fetch, and will be the same for all instructions
With this implementation, fetch and execute of the add instruction takes 6 clock cycles
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11. Concrete RTN for Arithmetic Instructions: addi
Abstract RTN:
addi (:= op= 13) ® R[ra] ¬ R[rb] + c2á16..0ñ {2's complement sign extend} : A L U C á 3 1 . ñ 2 R I M T o m e r y s u b t D P B - i g n a l p
Concrete RTN for addi:
Step RTN
T0. MA ¬ PC: C ¬ PC + 4;
T1. MD ¬ M[MA]; PC ¬ C;
T2. IR ¬ MD;
T3. A ¬ R[rb];
T4. C ¬ A + c2á16..0ñ {sign ext.};
T5. R[ra] ¬ C;
Instr Fetch
Instr Exec.
Differs from add only in step T4
Establishes requirement for sign extend hardware
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12. Abstract and Concrete RTN for Load and Store
ld (:= op= 1) ® R[ra] ¬ M[disp] :
st (:= op= 3) ® M[disp] ¬ R[ra] :
where
dispá31..0ñ := ((rb=0) ® c2á16..0ñ {sign ext.} :
(rb¹0) ® R[rb] + c2á16..0ñ {sign extend, 2's comp.} ) :
Tbl 4.3 The ld and st (load/store register from memory) Instructions
Step
RTN for ld
RTN for st
T0–T2
Instruction fetch T3
A←((rb=0)→0: (rb≠ 0) → R[rb]); T4 T5
MA←C; T6
MD ← M[MA];
MD ← R[ra]; T7
R[ra] ← MD
MA[MD] ← MD;
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13. Notes for Load and Store RTN
Steps T0 through T2 are the same as for add and addi, and for all instructions
In addition, steps T3 through T5 are the same for ld and st, because they calculate disp
A way is needed to use 0 for R[rb] when rb = 0
15-bit sign extension is needed for IRá16..0ñ
Memory read into MD occurs at T6 of ld
Write of MD into memory occurs at T7 of st
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14. Concrete RTN for Conditional Branch
br (:= op= 8) ® (cond ® PC ¬ R[rb]):
cond := ( c3á2..0ñ=0 ® 0: never
c3á2..0ñ=1 ® 1: always
c3á2..0ñ=2 ® R[rc]=0: if register is zero
c3á2..0ñ=3 ® R[rc]¹0: if register is nonzero
c3á2..0ñ=4 ® R[rc]á31ñ=0: if positive or zero
c3á2..0ñ=5 ® R[rc]á31ñ=1 ): if negative
Tbl 4.4 The Branch Instruction, br
Step RTN
T0–T2 Instruction fetch
T3 CON ¬ cond(R[rc]);
T4 CON ® PC ¬ R[rb];
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15. Notes on Conditional Branch RTN
c3á2..0ñ are just the low-order 3 bits of IR
cond() is evaluated by a combinational logic circuit having inputs from R[rc] and c3á2..0ñ
The one bit register CON is not accessible to the programmer and only holds the output of the combinational logic for the condition
If the branch succeeds, the program counter is replaced by the contents of a general register
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16. Abstract and Concrete RTN for SRC: Shift Right
shr (:= op = 26) ® R[ra]á31..0ñ ¬ 0) # R[rb]á31..nñ :
n := ( (c3á4..0ñ = 0) ® R[rc]á4..0ñ : Shift count in register
(c3á4..0ñ ¹ 0) ® c3á4..0ñ ): or constant field of instruction
Tbl 4.5 The shr Instruction
Step Concrete RTN
T0–T2 Instruction fetch
T3 n ¬ IRá4..0ñ;
T4 (n = 0) ® (n ¬ R[rc]á4..0 ñ);
T5 C ¬ R[rb];
T6 Shr (:= (n ¹ 0) ® (Cá31..0 ñ ¬ 0#Cá31..1 ñ: n ¬ n - 1; Shr) );
T7 R[ra] ¬ C;
step T6 is repeated n times
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17. Notes on SRC Shift RTN In the abstract RTN, n is defined with “:=“
In the concrete RTN, it is a physical register
n not only holds the shift count but is used as a counter in step T6
Step T6 is repeated n times as shown by the recursion in the RTN
The control for such repeated steps will be treated later
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18. Data Path Implementation
The designs of the data path involves decisions at several level of abstraction:
Microarchitecture (highest level of abstraction):
Basic registers and interconnections of an implementation are laid out.
Type of the interconnecting bus to use.
Number and kind of interconnecting buses:
1-bus, 2-bus and 3-bus architectures.
Design of ALU and CPU-to-memory interface.
Separate incrementer for PC.
Type of flip-flops to be used to implement registers, etc.
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19. Data Path Implementation
Low-level decisions relate to the selection of an implementation domain for the registers and buses.
These decisions determine what signals must be applied to the data path hardware to cause it to carry out its actions.
These control signals:
gate data onto buses,
strobe values into flip-flops,
specify ALU function,
control memory activity, etc.
The control signals form the interface between the data path and the control unit, and are thus an important part of data path design.
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20. Data Path/Control Unit Separation
Interface between data path and control consists of gate and strobe signals
A gate selects one of several values to apply to a common point, say a bus
A strobe changes the values of the flip-flops in a register to match new inputs
The type of flip-flop used in registers has much influence on control and some on data path
Latch: simpler hardware, but more complex timing
Edge triggering: simpler timing, but about twice the hardware
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21. Reminder on Latch- and Edge-Triggered Operation
Latch output follows input while strobe is high D D Q C C Q
Edge-triggering samples input at edge time D D Q C C Q
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22. Logic Design for the 1-Bus SRC
In the following section a design of SRC will be developed down to the gate level.
Overview of the design
Develop each of the blocks at the gate level.
Design of the data path hardware
Memory interface
Design of IR hardware from which most of the control signals are developed.
Design of the control unit.
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23. Concrete RTN lets us add detail to the data path
Fig 4.3 More Complete View of Registers and Buses in the 1-Bus SRC Design, Including Some Control Signals F i g u r e 4 . 4
Concrete RTN lets us add detail to the data path
Instruction register logic and new paths
Condition bit flip-flop
Shift count register 3 1 á 3 1 . . ñ 3 1 R P C 3 2 3 2 - b i t 3 2 C O N g e n e r a l D Q C O N i n p u r p o s e C o n d F i g u r e 4 . 9 r e g i s t e r s l o g i c O p 5 5 c 3 á 2 . . ñ R e g i s t e r s e l e c t S e l e c t l o g i c R 3 1 I R F i g u r e 4 . 5 S e l e c t l o g i c A 3 2 c 1 á 3 1 . . ñ 3 2 c 2 á 3 1 . . ñ A B M A T o m e m o r y s u b s y s t e m F i g u r e 4 . 6 A L U M D C 4 á 4 . . ñ
Keep this slide in mind as we discuss concrete RTN of instructions. C n n = F i g u r e 4 . 8 D e c r e m e n t S h i f t c o u n t , n F i g u r e 4 . 7
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24. Gate-Level Design of SRC
In this section we will fill in the blocks shown in Figure 4.3 presented in previous slide.
Describe control signals that implement the RTN of the instructions in the preceding discussion.
Start with Register File
Extraction of c1 and c2 constant fields and the opcode field from instruction register.
Design of the memory interface.
Describe the instruction fetch and the add, addi ,ld and st instruction’s control sequences.
Design of n – shift count register and the shr instruction
Conclude with description of the condition register and the br instruction.
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25. The Register File
Block 4.4 of the Figure 4.3 presented in more detail the next slide shows the gate-level design of the general register file R[0..31]<31..0>, .
The ra, rb, and rc fields in the IR, , specify source and destination registers.
The control signals Gra, Grb, and Grc, , gate one of the three registers fields into the 5-32 decoder, , that decodes the register field to 1 of the 32 selected lines.
Decoder outputs can be used to:
Either strobe, , or
Gate, , the bus into or out of the selected register.
A particular operation is controlled with Rin or Rout control signals.
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26. The Register File
The control signal BAout (BA for base address) is used to accommodate the calculation of the base address from which the displacement address is calculated.
disp<31..0> :=
((rb=0) → c2<16..0> {sign ext.} :
(rb≠0) → R[rb] + c2<16..0> {sign extend, 2's comp.} ) :
The BAout signal gates 0’s onto the bus if R0 is selected , , or the selected register’s contents if one of R1,..R31 is selected, .
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27. Fig 4.4 The Register File and Its Control Signals3 1 2 5 R S e l c t o g i I 7 O p r a b G 6 - n u s F m 4 . D Q d B A
<
> 8
. . .
Rout gates selected register onto bus
Rin strobed selected register from bus
BAout differs from Rout by gating 0 when R[0] is selected
BA = Base Address
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28. Iá21ñ is the sign bit of C1 that must be extended
Fig 4.5 Extracting c1, c2, and OP from the Instruction Register, IR<31...0>
c1<21..0> := IR<21..0>: Long displacement field
c2<16..0> := IR<16..0>: Short displacement or immediate field
Iá21ñ is the sign bit of C1 that must be extended
Iá16ñ is the sign bit of C2 that must be extended
Sign bits are fanned out from one to several bits and gated to bus
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29. The CPU–Memory Interface:
Memory Address and Memory Data Registers:
MA<31...0> and MD<31...0>
MD is loaded from memory or from CPU bus
MD can drive CPU bus or memory bus
Figure 4.6 3 2 3 2  M D b u s 3 2  3 2 3 2 D Q M D r d M D R e a d 3 2 3 2 F r o m F i g u r e 4 . 3  Q W r i t e  S t r o b e M D á 3 1 . . ñ D o n e M A T o m e m o r y s u b s y s t e m 3 2 3 2 d a t a á 3 1 . . ñ M D M D w r M e m o r y M D o u t b u s  3 2 3 2 a d d r á 3 1 . . ñ D Q M A
MA – continuously connected
To the memory address bus! M A i n Q M A á 3 1 . . ñ C P U b u s
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30. Fig 4.7 The ALU and Its Associated Registers
Combinational Circuit with 11 Control Signals: ADD, SUB, AND, OR, SHR, SHRA, SHL, SHC, NOT, C=B, and INC4. A F r o m i g u e 4 . 3 C n D S U B N O T = I Q 2 t 1 L
. . .
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31. From Concrete RTN to Control Signals
The Control Sequence for Instruction Fetch
Tbl 4.6 The Instruction Fetch
Step Concrete RTN Control Sequence
T0 MA ¬ PC: C ¬ PC + 4; PCout, MAin, INC4, Cin
T1 MD ¬ M[MA]: PC ¬ C; Read, Cout, PCin, Wait
T2 IR ¬ MD; MDout, IRin
T3 Instruction_execution
The register transfers are the concrete RTN
The control signals that cause the register transfers make up the control sequence
Wait prevents the control from advancing to step T3 until the memory asserts Done
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32. Control Steps, Control Signals, and Timing
Within a given time step, the order in which control signals are written is irrelevant
In step T0, Cin, INC4, MAin, PCout  PCout, MAin, INC4, Cin
The only timing distinction within a step is between gates and strobes
The memory read should be started as early as possible to reduce the wait
MA must have the right value before being used for the read
Depending on memory timing, Read could be in T0
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33. Control Sequence for the SRC add
add (:= op = 12) ® R[ra] ¬ R[rb] + R[rc]:
Tbl 4.7 The add Instruction
Step Concrete RTN Control Sequence
T0 MA ¬ PC: C ¬ PC + 4; PCout, MAin, INC4, Cin
T1 MD ¬ M[MA]: PC ¬ C; Cout, PCin, Read, Wait
T2 IR ¬ MD; MDout, IRin
T3 A ¬ R[rb]; Grb, Rout, Ain
T4 C ¬ A + R[rc]; Grc, Rout, ADD, Cin
T5 R[ra] ¬ C; Cout, Gra, Rin, End
Note the use of Gra, Grb, and Grc to gate the correct 5-bit register select code to the registers
End signals the control to start over at step T0
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34. Control Sequence for the SRC addi
addi (:= op= 13) ® R[ra] ¬ R[rb] + c2á16..0ñ {2’s comp., sign ext.} :
Tbl 4.8 The addi Instruction
Step Concrete RTN Control Sequence
T0. MA ¬ PC: C ¬ PC + 4; PCout, MAin, Inc4, Cin
T1. MD ¬ M[MA]; PC ¬ C; Cout, PCin, Read, Wait
T2. IR ¬ MD; MDout, IRin
T3. A ¬ R[rb]; Grb, Rout, Ain
T4. C ¬ A + c2á16..0ñ {sign ext.}; c2out, ADD, Cin
T5. R[ra] ¬ C; Cout, Gra, Rin, End
The c2out signal sign extends IRá16..0ñ and gates it to the bus
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35. Control Sequence for the SRC st
st (:= op = 3) ® M[disp] ¬ R[ra] :
dispá31..0ñ :=
((rb=0) ® c2á16..0ñ {sign extend} :
(rb¹0) ® R[rb] + c2á16..0ñ {sign extend, 2’s complement}) ;
The st Instruction
Step Concrete RTN Control Sequence
T0–T2 Instruction fetch Instruction fetch
T3 A ¬ (rb=0) ® 0: rb ¹ 0 ® R[rb]; Grb, BAout, Ain
T4 C ¬ A + c2á16..0ñ {sign-extend}; c2out, ADD, Cin
T5 MA ¬ C; Cout, MAin
T6 MD ¬ R[ra]; Gra, Rout, MDin, Write
T7 M[MA] ¬ MD; Wait, End
Note BAout in T3 compared to Rout in T3 of addi
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36. Control Sequence for the SRC ld
ld (:= op = 1) ® R[ra] ¬ M[disp] :
dispá31..0ñ :=
((rb=0) ® c2á16..0ñ {sign extend} :
(rb¹0) ® R[rb] + c2á16..0ñ {sign extend, 2’s complement}) ;
The ld Instruction
Step Concrete RTN Control Sequence
T0–T2 Instruction fetch Instruction fetch
T3 A ¬ (rb=0) ® 0: rb ¹ 0 ® R[rb]; Grb, BAout, Ain
T4 C ¬ A + c2á16..0ñ {sign-extend}; c2out, ADD, Cin
T5 MA ¬ C; Cout, MAin
T6 MD ¬ M[MA]; Read, Wait, MDrd, strobe
T7 R[ra] ¬ MD; Gra, Rin, MDout End
Note that control signals MDrd and strobe as depicted from Figure 4.6, are being used to strobe data form memory bus into MD. However, they are not shown (e.g. they are shown in red) in the table above because it is assumed that the memory system is responsible for asserting these signals.
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37. The Shift Counter
The concrete RTN for shr relies upon a 5-bit register to hold the shift count
It must load, decrement, and have an “= 0” test
Fig 4.8 B u s F r o m F i g u r e 4 . 3 á 4 . . ñ 5 4 á 4 . . ñ n n = n : s h i f t c o u n t 3 2 D e c r 5 - b i t d o w n c o u n t e r D e c r e m e n t S h i f t c o u n t , n L d n = Q 4 . . Q X Y
X⊕Y 1 á 3 1 . . ñ n =
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38. Control Sequence for the SRC shr
Looping
Step Concrete RTN Control Sequence
T0–T2 Instruction fetch Instruction fetch
T3 n ¬ IRá4..0ñ; c1out, Ld
T4 (n=0) ® (n ¬ R[rc]á4..0ñ); n=0 ® (Grc, Rout, Ld)
T5 C ¬ R[rb]; Grb, Rout, C=B, Cin
T6 Shr (:= (n¹0) ® n¹0 ® (Cout, SHR, Cin,
(Cá31..0ñ ¬ 0#Cá31..1ñ: Decr, Goto6)
n ¬ n-1; Shr) );
T7 R[ra] ¬ C; Cout, Gra, Rin, End
Conditional control signals and repeating a control step are new concepts
Barrel shifter design enables 1 cycle shift.
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39. Branching This is equivalent to the logic expression
cond := ( c3á2..0ñ=0 ® 0:
c3á2..0ñ = 1 ® 1:
c3á2..0ñ = 2 ® R[rc] = 0:
c3á2..0ñ = 3 ® R[rc] ¹ 0:
c3á2..0ñ = 4 ® R[rc]á31ñ = 0:
c3á2..0ñ = 5 ® R[rc]á31ñ = 1 ):
This is equivalent to the logic expression
cond = (c3á2..0ñ = 1) Ú
(c3á2..0ñ = 2)Ù(R[rc] = 0) Ú
(c3á2..0ñ = 3)ÙØ(R[rc] = 0) Ú
(c3á2..0ñ = 4)ÙØR[rc]á31ñ Ú
(c3á2..0ñ = 5)ÙR[rc]á31ñ
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40. Computation of the Conditional Value CONR á 2 . . ñ 3 B u s D e c o d e r F r o m F i g u r e 4 . 3 5 4 3 2 1 D Q C O N 1 C O N 3 2 i n 3 2 = C o n d l o g i c D Q c 3 á 2 . . ñ á 3 1 ñ C O N C O N Q i n
< á 3 1 . . ñ
NOR gate does “= 0” test of R[rc] on processor bus
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41. Control Sequence for SRC Branch br
br (:= op = 8) ® (cond ® PC ¬ R[rb]):
Step Concrete RTN Control Sequence
T0–T2 Instruction fetch Instruction fetch
T3 CON ¬ cond(R[rc]); Grc, Rout, CONin
T4 CON ® PC ¬ R[rb]; Grb, Rout, CON ® PCin, End
Condition logic is always connected to CON, so R[rc] only needs to be put on bus in T3
Only PCin is conditional in T4 since gating R[rb] to bus makes no difference if it is not used
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42. Summary of the Design Process
Informal description Þ
formal RTN description Þ
block diagram architecture Þ
concrete RTN steps Þ
hardware design of blocks Þ
control sequences Þ
control unit and timing
At each level, more decisions must be made
These decisions refine the design
Also place requirements on hardware still to be designed
The nice one-way process above has circularity
Decisions at later stages cause changes in earlier ones
Happens less in a textbook development than in reality because
Can be fixed on re-reading
It can be confusing to students.
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43. Clocking the Data Path:
Register Transfer Timing
tR2valid is the period from begin of gate signal till inputs to R2 are valid
tcomb is delay through combinational logic, such as ALU or cond logic S o u r c e B u s L o g i c D e s t i n a t i o n r e g i s t e r g a t e b l o c k r e g i s t e r n - b i t b u s D Q D Q n C o m b i n a t i o n a l R 1 R R 2 l o g i c o u t C K Q C K Q R i n C i r c u i t G a t e B u s p r o p . A L U , L a t c h p r o p a g a t i o n p r o p . d e l a y , e t c . p r o p . d e l a y t i m e , t d e l a y , d e l a y , b p t t t g c o m b l G a t e s i g n a l : L a t c h h o l d t i m e , t h R o u t L a t c h s e t u p t i m e , t s u S t r o b e s i g n a l : t R R 2 v a l i d i n M i n i m u m p u l s e w i d t h , t w M i n i m u m c l o c k p e r i o d , t m i n
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44. Signal Timing on the Data Path
Several delays occur in getting data from R1 to R2
Gate delay through the 3-state bus driver—tg
Worst case propagation delay on bus—tbp
Delay through any logic, such as ALU—tcomb
Set up time for data to affect state of R2—tsu
Data can be strobed into R2 after this time
tR2valid = tg + tbp + tcomb + tsu
Diagram shows strobe signal in the form for a latch. It must be high for a minimum time—tw
There is a hold time, th, for data after strobe ends
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45. Effect of Signal Timing on Minimum Clock Cycle
A total latch propagation delay is the sum
tl = tsu + tw + th
All above times are specified for latch
th may be very small or zero
The minimum clock period is determined by finding longest path from ff output to ff input
This is usually a path through the ALU
Conditional signals add a little gate delay
Using this path, the minimum clock period is
tmin = tg + tbp + tcomb + tl
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46. Latches Versus Edge-Triggered or Master-Slave Flip-Flops
During the high part of a strobe a latch changes its output
If this output can affect its input, an error can occur
This can influence even the kind of concrete RTs that can be written for a data path
If the C register is implemented with latches, then C ¬ C + MD; is not legal
If the C register is implemented with master-slave or edge-triggered flip-flops, it is OK
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47. The Control Unit
The control unit’s job is to generate the control signals in the proper sequence
Things the control signals depend on
The time step Ti
The instruction opcode (for steps other than T0, T1, T2)
Some few data path signals like CON, n=0, etc.
Some external signals: reset, interrupt, etc. (to be covered)
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48. The Control Unit The components of the control unit are:
a time state generator,
instruction decoder, and
combinational logic to generate control signals
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49. Control Unit Detail with Inputs and Outputs
Fig 4.11 M a s t e r c l o k S E n b p g C u W i D d R L O h f m I x G T 1 2 4 – N = P A
. . .
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50. Synthesizing Control Signal Encoder Logic
Step C o n t r l S e q u c
T0. P , M A i I 4 R a d
T1. W
T2. D G b E
T3.
T4. 2
T5. s B
T6.
T7. h 1 L = ( ) H 7
Step
T3.
T4.
T5.
Design process:
Comb through the entire set of control sequences.
Find all occurrences of each control signal.
Write an equation describing that signal.
Example: Gra = T5·(add + addi) + T6·st + T7·shr + ...
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51. Use of Data Path Conditions in Control Signal Logic
Step C o n t r l S e q u c
T0. P , M A i I 4 R a d
T1. W
T2. D
T3. G b
T4.
T5. E 2 s B
T6.
T7. h 1 L = ( ) H 7
Example: Cout = T1 + T5·(add+addi+st+…) + … Grc = T4·add + T4·(n=0)·shr + ...
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52. Generation of the logic for Cout and Gra
Fig 4.12 C o u t G r a T 5 7 l d 1 i
. . .
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53. Branching in the Control Unit
Fig 4.13
3-state gates allow 6 to be applied to counter input
Reset will synchronously reset counter to step T0 M c k E n a b l e S t e p g e n e r a t o r r e C o n t r o l t C o u n t l n n u s t e p o d e c o d e r C 4 L o a d 1 1 R e s e t G o t o 6
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54. Enable = Run(SDone+Wait+(R+W))
The Clocking Logic:
Start, Stop, and Memory Synchronization
Fig Mck is master clock oscillator 1 R u n ( G ) S t r t ( E ) J Q 2 D o n e ( E ) D Q S t o p ( C ) K Q S D o n e ( G ) M c k ( I ) Q 4 E n a b l e ( G ) W a i t ( C )
Enable = Run(SDone+Wait+(R+W)) R e a d ( C ) J Q R ( G ) 3 K Q T o m e m o r y s y s t e m L e g e n d W r i t e ( C ) J Q W ( G ) E – E x t e r n a l G – G e n e r a t e d C – C o n t r o l s i g n a l K Q I – I n t e r n a l
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55. The Complete 1-Bus Design of SRC
High-level architecture block diagram
Concrete RTN steps
Hardware design of registers and data path logic
Revision of concrete RTN steps where needed
Control sequences
Register clocking decisions
Logic equations for control signals
Time step generator design
Clock run, stop, and synchronization logic
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56. Other Architectural Designs
Other Architectural Designs Will Require a Different RTN
More data paths allow more things to be done in one step
Consider a two bus design
By separating input and output of ALU on different buses, the C register is eliminated
Steps can be saved by strobing ALU results directly into their destinations
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57. The 2-Bus SRC Microarchitecture
Fig 4.15
Bus A carries data going into registers
Bus B carries data being gated out of registers
ALU function C=B is used for all simple register transfers A L U C B b u s ( “ O t ” ) I n M e m o r y 3 2 1 R g a l p i P D
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58. The 2-Bus add Instruction
Tbl 4.13
Step Concrete RTN Control Sequence
T0 MA ¬ PC; PCout, C = B, MAin, Read
T1 PC ¬ PC + 4: MD ¬ M[MA];PCout, INC4, PCin, Wait
T2 IR ¬ MD; MDout, C = B, IRin
T3 A ¬ R[rb]; Grb, Rout, C = B, Ain
T4 R[ra] ¬ A + R[rc]; Grc, Rout, ADD, Sra, Rin, End
Note the appearance of Grc to gate the output of the register rc onto the B bus and Sra to select ra to receive data strobed from the A bus
Two register select decoders will be needed
Transparent latches will be required at step T2
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59. Performance and Design
Where
IC - instruction count:
Assume it will not change when going from 1-bus to 2-bus design.
CPI – number of clock cycles per instruction.
Assume that all instruction will require less number of clock cycles to execute just like ld (load) instruction requiring T7 instead of T8 clock cycles
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60. Speedup By Going to 2 Buses
Assume for now that IC and t don’t change in going from 1 bus to 2 buses
Naively assume that CPI goes from 8 to 7 clocks. Thus:
Class Problem:
How will this speedup change if clock period of 2-bus machine is increased by 10% compared to 1-bus architecture?
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61. 3-Bus Architecture Shortens Sequences Even More:
A 3-bus architecture allows both operand inputs and the output of the ALU to be connected to buses
Both the C output register and the A input register are eliminated
Careful connection of register inputs and outputs can allow multiple RTs in a step
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62. The 3-Bus SRC Design
Fig 4.16
A-bus is ALU operand 1, B-bus is ALU operand 2, and C-bus is ALU output
Note MA input connected to the B-bus A L U C b u s B M e m o r y 3 2 1 R g n a l p i t I P D
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63. The 3-Bus add Instruction
Tbl 4.15
Step Concrete RTN Control Sequence
T0 MA ¬ PC: MD ¬ M[MA]: PCout, MAin, INC4, PCin,
PC ¬ PC + 4; Read, Wait
T1 IR ¬ MD; MDout, C = B, IRin
T2 R[ra] ¬ R[rb] + R[rc]; GArc, RAout, GBrb, RBout,
ADD, Sra, Rin, End
Note the use of 3 register selection signals in step T2: GArc, GBrb, and Sra
In step T0, PC moves to MA over bus B and goes through the ALU INC4 operation to reach PC again by way of bus C
PC must be edge-triggered or master-slave
Once more MA must be a transparent latch
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64. Performance and Design
How does going to three buses affect performance?
Assume average CPI goes from 8 to 4, while t increases by 10%:
Assume now that:
memory access takes 3 cycles to complete instead of 1.
20% of instructions are loads,
Processor does not wait on stores:
CPI1-bus=8+2(instruction fetch)+0.2x2(data fetch)=10.4
CPI3-bus=4+2(instruction fetch)+0.2x2(data fetch)=6.4
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65. Amdahl’s Law
Empirical law that gives the upper bound on systems performance enhancement if one component of the system is improved.
Definitions:
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66. Amdahl’s Law System Speed-up (≡f – fraction parameter)
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67. Processor Reset Function
Reset sets program counter to a fixed value
May be a hardwired value, or
contents of a memory cell whose address is hardwired
The control step counter is reset
Pending exceptions are prevented, so initialization code is not interrupted
It may set condition codes (if any) to known state
It may clear some processor state registers
A “soft” reset makes minimal changes:
PC,
Interrupt flags.
A “hard” reset initializes more processor state (other registers in addition to PC).
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68. SRC Reset Capability We specify both a hard and soft reset for SRC
The Strt signal will do a hard reset
It is effective only when machine is stopped
It resets the PC to zero
It resets all 32 general registers to zero
The Soft Reset signal is effective when the machine is running
It sets PC to zero
It restarts instruction fetch
It clears the Reset signal
Actions are described in instruction_interpretation
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69. Abstract RTN for SRC Reset and Start
Processor State
Strt: Start signal
Rst: External reset signal
instruction_interpretation := (
¬Run∧Strt → (Run ← 1: PC, R[0..31] ← 0);
Run∧¬Rst → (IR ← M[PC]: PC ← PC + 4; Instruction_execution):
Run∧Rst → ( Rst ← 0: PC ← 0); instruction_interpretation ):
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70. Resetting in the Middle of Instruction Execution
The abstract RTN implies that reset takes effect after the current instruction is done
To describe reset during an instruction, we must go from abstract to concrete RTN
Questions for discussion:
Why might we want to reset in the middle of an instruction?
How would we reset in the middle of an instruction?
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71. The add Instruction with Reset Processing
Tbl 4.17
Step Concrete RTN
T0 ØRst ® (MA ¬ PC: C ¬ PC + 4):
Rst ® (Rst ¬ 0: PC ¬ 0: T ¬0):
T1 ØRst ® (MD ¬ M[MA]: P ¬ C):
Rst ® (Rst ¬ 0: PC ¬ 0: T ¬ 0):
T2 ØRst ® (IR ¬ MD):
T3 ØRst ® (A ¬ R[rb]):
T4 ØRst ® (C ¬ A + R[rc]):
T5 ØRst ® (R[ra ] ¬ C):
See the textbook for the corresponding control signals
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72. Control Sequences Including the Reset Function
Step Control Sequence
T0 ØReset ® (PCout, MAin, Inc4, Cin, Read):
Reset ® (ClrPC, ClrR, Goto0):
T1 ØReset ® (Cout, PCin, Wait):
• • •
ClrPC clears the program counter to all zeros, and ClrR clears the 1-bit Reset flip-flop
Because the same reset actions are in every step of every instruction, their control signals are independent of time step or opcode
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73. General Comments on Exceptions
An exception is an event that causes a change in the program specified flow of control
Because normal program execution is interrupted, they are often called interrupts
We will use exception for the general term and use interrupt for an exception caused by an external event, such as an I/O device condition
The usage is not standard. Other books use these words with other distinctions, or none
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74. Combined Hardware/Software Response to an Exception
The system must control the type of exceptions it will process at any given time
The state of the running program is saved when an allowed exception occurs
Control is transferred to the correct software routine, or “handler,” for this exception
This exception, and others of less or equal importance, are disallowed during the handler
The state of the interrupted program is restored at the end of execution of the handler
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75. Hardware Required to Support Exceptions
To determine relative importance, a priority number is associated with every exception
Hardware must save and change the PC, since without it no program execution is possible
Hardware must disable the current exception lest is interrupt the handler before it can start
Address of the handler is called the exception vector and is a hardware function of the exception type
Exceptions must access a save area for PC and other hardware saved items
Choices are special registers or a hardware stack
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76. New Instructions Needed to Support Exceptions
An instruction executed at the end of the handler must reverse the state changes done by hardware when the exception occurred
There must be instructions to control what exceptions are allowed
The simplest of these enable or disable all exceptions
If processor state is stored in special registers on an exception, instructions are needed to save and restore these registers
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77. Kinds of Exceptions System reset
Exceptions associated with memory access
Machine check exceptions
Data access exceptions
Instruction access exceptions
Alignment exceptions
Program exceptions
Miscellaneous hardware exceptions
Trace and debugging exceptions
Non-maskable exceptions
External exceptions—interrupts
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78. An Interrupt Facility for SRC
The exception mechanism for SRC handles external interrupts
There are no priorities, but only a simple enable and disable mechanism
The PC and information about the source of the interrupt are stored in special registers
Any other state saving is done by software
The interrupt source supplies 8 bits that are used to generate the interrupt vector
It also supplies a 16-bit code carrying information about the cause of the interrupt
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79. SRC Processor State Associated with Interrupts
Processor interrupt mechanism
ireq: Interrupt request signal
iack: Interrupt acknowledge signal
IE: 1-bit interrupt enable flag
IPCá31..0ñ: Storage for PC saved upon interrupt
IIá31..0ñ: Information on source of last interrupt
Isrc_infoá15..0ñ: Information from interrupt source
Isrc_vectá7..0ñ: Type code from interrupt source
Ivectá31..0ñ:=
From Device ®
To Device ®
Internal ®
to CPU ®
Ivectá31..0ñ
Isrc_vectá7..0ñ
0000 31 12 11 4 3
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80. SRC Instruction Interpretation Modified for Interrupts
(ØRunÙStrt ® Run ¬ 1:
RunÙØ(ireqÙIE) ® (I ¬ M[PC]: PC ¬ PC + 4; instruction_execution):
RunÙ(ireqÙIE) ® (IPC ¬ PC á31..0ñ:
IIá15..0ñ ¬ Isrc_infoá15..0ñ: iack ¬ 1:
IE ¬ 0: PC ¬ Ivectá31..0 ñ; iack ¬ 0);
instruction_interpretation);
If interrupts are enabled, PC and interrupt information are stored in IPC and II, respectively
With multiple requests, external priority circuit (discussed in later chapter) determines which vector and information are returned
Interrupts are disabled
The acknowledge signal is pulsed
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81. SRC Instructions to Support Interrupts
Return from interrupt instruction
rfi (:= op = 29 ) ® (PC ¬ IPC: IE ¬ 1):
Save and restore interrupt state
svi (:= op = 16) ® (R[ra] á15..0ñ ¬ IIá15..0 ñ: R[rb] ¬ IPCá31..0ñ):
ri (:= op = 17) ® (II á15..0ñ ¬ R[ra]á15..0 ñ : IPCá31..0 ñ ¬ R[rb]):
Enable and disable interrupt system
een (:= op = 10 ) ® (IE ¬ 1):
edi (:= op = 11 ) ® (IE ¬ 0):
The 2 rfi actions (PC ¬ IPC: IE ¬ 1): are indivisible; can’t een and branch to accomplish the same result.
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82. Concrete RTN for SRC Instruction Fetch with Interrupts
Step Ø(ireqÙIE) Concrete RTN (ireqÙIE)
T0 (Ø(ireqÙIE) ® ( (ireqÙIE) ® (IPC ¬ PC: II ¬ Isrc_info:
MA ¬ PC: C ¬ PC+4): IE ¬ 0: PC¬ á7..0ñ#00:
Iack¬1; Iack ¬ 0: End);
T1 MD ¬ M[MA] : PC ¬ C;
T2 IR ¬ MD;
PC could be transferred to IPC over the bus
II and IPC probably have separate inputs for the externally supplied values
iack is pulsed, described as ¬1; ¬0, which is easier as a control signal than in RTN
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83. Exceptions During Instruction Execution
Some exceptions occur in the middle of instructions
Some CISCs have very long instructions, like string move
Some exception conditions prevent instruction completion, like uninstalled memory
To handle this sort of exception, the CPU must make special provision for restarting
Partially completed actions must be reversed so the instruction can be re-executed after exception handling
Information about the internal CPU state must be saved so that the instruction can resume where it left off
We will see that this problem is acute with pipeline designs—always in middle of instructions
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84. Recap of the Design Process:
The Main Topic of Chapter 4
SRC
Informal description
Chapter 2
Formal RTN description
Block diagram architecture
Concrete RTN steps
Chapter 4
Hardware design of blocks
Control sequences
Control unit and timing
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