1. Fernando J. Barbosa barbosa@jlab.org
F1TDC Status Update Hall D Collaboration Meeting Indiana University – Bloomington, IN May 20-22, 2004
Fernando J. Barbosa
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2. Team Members Ed Jastrzembski James Proffitt Design F. J. Barbosa
Layout Jeff Wilson
Production Chris Cuevas
Software David Abbott
QC & Rework Bill Gunning
Signal Hub Mark Taylor
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3. A Brief History
Discussions on a high resolution TDC for use in Hall D started in late 1999.
Other JLAB users showed interest in a high resolution TDC - design work started in mid 2000.
Two fully functional prototypes tested in Results were presented at the 2002 IEEE NSS-MIC.
Production of 50 units has been completed for Hall C and other users at JLAB in early 2004.
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4. F1TDC Specifications 11/15/2018 Packaging 6U VME64x
Inputs Differential ECL (110 Ohm)
pS LSB
32 60 pS LSB
Control START, SYNCRES, TRIGGER
Front Panel – Differential ECL (110 Ohm)
Backplane – Differential LVPECL (110 Ohm)
Clock Differential LVPECL (110 Ohm) – 40 MHz
Internal, Front Panel, Backplane
Dynamic 7.8 uS (for 120 pS LSB)
Range 3.9 uS (for 60 pS LSB)
Standard Less than 0.9 LSB
Deviation
INL 0 LSB
DNL % LSB
Acquisition Trigger Matching w/ Zero suppression
Programmable Trigger Window and Latency
FIFO 1 M TDC Data Words
Interface 32-bit VME Block Transfers (>20 Mbyte/s)
64-bit VME Block Transfers (>40 Mbyte/s)
Power 0.5A
0.4A
7.3A
1.8A
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5. Project Status A few ECOs and rework performed after receipt of units.
All 50 production units tested after a burn-in period of at least 72 hours:
34 Pass, 16 Need Further Checks
64-bit data readout available (40 Mbytes/s).
Multi-block readout functioning properly (multiple boards – single logical read).
Backplane signal distribution hub has been designed. Layout is close to completion.
User’s Manual available online at
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6. Project Status (cont.) Two software initiatives:
Functional Testing – single board lab bench testing.
For Users – library created to be used within VxWorks.
Software library contains code to access, initialize, configure, control, and readout of a crate full of F1TDC boards (up to 20).
Transparency – the user does not need intimate knowledge of the F1 chip control registers, timing and order of programming.
Library designed to be functionally independent but intended for CODA users:
# Setup F1TDC
f1Clear(F1_SLOT);
f1EnableData(F1_SLOT,0xff); /*all 8 chips*/
f1SetBlockLevel(F1_SLOT,1); /*read 1 event at a time*/
f1EnableBusError(F1_SLOT);
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7. Schedule Project on target to be completed by early July 2004.
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