1. Topics
16 x 16 multiplier example.

2. The FPGA design process
Translation from HDL.
(synthesis, translation)
Logic synthesis.
(mapping)
Placement and routing.
(place and route)
Configuration generation.
(program file generation)

3. Design experiments Synthesize with no constraints.
Synthesize with timing constraint.
Tighten timing constraint.
Synthesize with placement constraints.

4. Post-translation simulation model
HDL model in terms of FPGA primitives.
Example:
X_LUT4 \p12_Madd__n0015_Mxor_Result_Xo<1>1 (
.ADR0(x_7_IBUF),
.ADR1(y_13_IBUF),
.ADR2(c12[7]),
.ADR3(row12[8]),
.O(row13[7]) );

5. Mapping report Design Summary -------------- Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of 4 input LUTs: out of 1, %
Logic Distribution:
Number of occupied Slices: out of %
Number of Slices containing only related logic: out of %
Number of Slices containing unrelated logic: out of %
*See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs: out of 1, %
Number of bonded IOBs: out of %
Total equivalent gate count for design: 3,006
Additional JTAG gate count for IOBs: 3,072
Peak Memory Usage: 64 MB

6. Static timing analysis report
Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" uS ;
items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is ns.

7. Static timing report: delays along paths
Data Sheet report:
All values displayed in nanoseconds (ns)
Pad to Pad
Source Pad |Destination Pad| Delay |
x<0> |p<0> | |
x<0> |p<10> | |
x<0> |p<11> | |
x<0> |p<12> | |

8. Routing report Phase 1: 1975 unrouted; REAL time: 11 secs
The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

9. Static timing after routing
Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" uS ;
items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is ns.

10. Timing constraint
Use timing constraint editor:

11. Post-map static timing report
Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 32 nS ;
items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is ns.

12. Post-routing static timing report
Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 32 nS ;
items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is ns.

13. Tighter timing constraints
Tighten requirement to 25 ns.
Post-place-route timing report:
Timing constraint: TS_P2P = MAXDELAY FROM TIMEGRP "PADS" TO TIMEGRP "PADS" 25 nS ;
items analyzed, 11 timing errors detected. (11 setup errors, 0 hold errors)
Maximum delay is ns.

14. Report on a violated path
Slack: ns (requirement - data path)
Source: y<0> (PAD)
Destination: p<30> (PAD)
Requirement: ns
Data Path Delay: ns (Levels of Logic = 31)
Data Path: y<0> to p<30>
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
K5.I Tiopi y<0>
y<0>
y_0_IBUF
SLICE_X2Y11.G net (fanout=31) y_0_IBUF
SLICE_X2Y11.Y Tilo c2<5>
p0_Madd__n0017_Mxor_Result_Xo<1>1
SLICE_X2Y11.F net (fanout=2) row1<6>
SLICE_X2Y11.X Tilo c2<5>
p1_Madd__n0019_Cout1
SLICE_X5Y16.F net (fanout=2) c2<5>
SLICE_X5Y16.X Tilo c3<5>
p2_Madd__n0019_Cout1
SLICE_X2Y18.G net (fanout=2) c3<5>
SLICE_X2Y18.Y Tilo row5<4>
p3_Madd__n0019_Mxor_Result_Xo<1>1

15. Power report Power summary: I(mA) P(mW)
Total estimated power consumption:
---
Vccint 1.50V:
Vccaux 3.30V:
Vcco V:
Inputs:
Logic:
Outputs:
Vcco
Signals:
Quiescent Vccaux 3.30V:
Quiescent Vcco V:
Thermal summary:
Estimated junction temperature: C
Ambient temp: 25C
Case temp: 35C
Theta J-A: 34C/W

16. Power report: decoupling capacitance
Decoupling Network Summary: Cap Range (uF) #
Capacitor Recommendations:
Total for Vccint :
: 1
: 1
: 2
---
Total for Vccaux :
Total for Vcco33 :
: 1
: 2
: 3
: 3

17. Improving area
Floorplanner window:
Chip
floorplan
LEs

18. Rat’s nest wiring

19. Routing editor view

20. Adding placement constraints
Must add attributes to the Verilog:
// synthesis attribute rloc of p0 is X0Y0
multrow p0(row0,x,y[1],y[0],c0,row1,c1);

21. Editing constraints
Use constraints editor to place constraints:

22. Design browser pane

23. Drag and drop constraints

24. Change the shape of constraints

25. Full set of placement constraints

26. Placement results

27. New timing report After placement constraints:
items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors)
Maximum delay is ns.
Compares to 31 ns for unconstrained placement.

28. Detailed routing constraints