1. Software Defined Radio Expanded
William Mullins, Srinu Munigala, Samir Rawashdeh, Daniel Steinberg
EE-587 Dr. Lumpp 22 APR 2008

2. Software Defined Radio Expanded
USRB Motherboard
22 Apr 2008
Software Defined Radio Expanded

3. Block diagram of the digital down-conversion and decimation stage
NOTE: there is effectively a single complex multipler. I.e., I2+jQ2 = (I1+jQ1) * exp(jwt). The effect of the NCO and multiplier are implemented using the CORDIC algorithm.
22 Apr 2008
Software Defined Radio Expanded

4. Block diagram of the digital up-conversion stage
NOTE: there is effectively a single complex multipler. I.e., I2+jQ2 = (I1+jQ1) * exp(jwt).
22 Apr 2008
Software Defined Radio Expanded

5. RFX2400 transmit signal path
In the diagram, G=gain and N=noise figure (dB) at 2.4 GHz
22 Apr 2008
Software Defined Radio Expanded

6. RFX2400 receive signal path
In the diagram, G=gain and N=noise figure (dB) at 2.4 GHz
22 Apr 2008
Software Defined Radio Expanded

7. The FPGA http://gnuradio.org/trac/wiki/UsrpFPGA
Features of the Altera Cyclone EP1C12Q240C8:
Les: 12,060
M4k RAM blocks (128 x 36 bits): 52
Total RAM bits: 239,616
PLLs: 2
Maximum user I/O pins: 173
The FPGA runs off a 64MHz clock with every internal component synchronous to that global clock. Due to the relatively high clocking frequency, everything within the FPGA is highly pipelined to achieve the highest speed possible.
22 Apr 2008
Software Defined Radio Expanded

8. Software Defined Radio Expanded
FPGA Block Diagram
There are two clocks: one for the USB bus (up to the FIFO) and one for the transmit chain itself. Channel 0 has a loop back facility. The Cascaded Integrator Comb (CIC) interpolation filter rate is controlled by the register FR_INTERP_RATE. The CORDIC transformation is currently disabled in svn HEAD.
22 Apr 2008
Software Defined Radio Expanded

9. Software Defined Radio Expanded
USB Interface
Describe how the host communicates with the USRP device?
22 Apr 2008
Software Defined Radio Expanded

10. Software Defined Radio Expanded
Links
Schematics and Layouts
svn co usrp-hw
FPGA information page
22 Apr 2008
Software Defined Radio Expanded