1. Leakage-Aware FPGA Re-synthesis
Victor Shih, Zhe Feng
EE 201C • UCLA Fall 2007

2. Motivation Our current FPGA re-synthesis framework optimizes area
For LUT-4 element, leakage depends on:
Configuration – 13.0% leakage difference between highest and lowest configurations
Input vector – 4.7% leakage difference between highest and lowest input vectors

3. Leakage by Configuration

4. Problem Formulation Develop leakage model
Consider configuration
Consider structure (LUT2,LUT3,LUT4…)
Consider input vector (future)
Use leakage model to evaluate and guide re-synthesis solutions process

5. Algorithm Extension Initial Circuit Circuit Library
re-synthesis window
Truth-table
SAT-Based
Boolean Matcher
Unsatisfiable
Satisfiable
Leakage Model