1. We will be studying the architecture of XC3000.
Xilinx
We will be studying the architecture of XC3000.
It is fabricated in CMOS technology
The chip is frequently referred to as Xilinx Logic Cell Array (LCA)
The first XC2000 series LCA was released in 1983.

3. (two-input NAND gates)
LCA3000 Series
The number of equivalent gates is
(two-input NAND gates)
Number of Configurable Logic Blocks (CLBs) is
Number of inputs to a CLB: 5
Flip-flops in a CLB: 2
I/O Blocks (IOBs):

4. XC3000 LCA architecture
The LCA architecture includes a fixed array of CLBs, input/output blocks (IOBs). The blocks can be connected by horizontal and vertical wire segments joined by the switch matrices. The programming elements inside the switch matrices establish the connections between the wire segments.

5. User logic is implemented by configuring the LCA’s components.
The Xilinx chip is reprogrammable since its programmability is based on the SRAM technolgy.

6. Configurable Logic Block (CLB)
The CLB of the 3000 series consists of two flip flops, a five-input look-up table (LUT) and many multiplexers (not accessible to the user). The LUT is a block of 32-bit RAM cells.
The LUT can realize any function of five variables or any two functions of four variables.

8. XC3000 CLB contd...
The CLB outputs x and y may be connected to the outputs of the LUT (or the function generator) directly or through flip-flops.
As the functions are implemented using a memory based LUT, propagation delay through the CLB is independent of the logic implemented.

9. XC3000 CLB contd... The flip-flops can be reset but not set
all flip-flops are automatically cleared after configuration
when ec (enable clock) is low, the flip-flops are forced to maintain their current values, ignoring the clock.

10. XC4000 CLB

11. IOB IOB provides interface between LCA and the external world.
There is one IOB for every programmable pin.
IOB can serve as input, output or tristate bidirectional path.
Input/output signals can be registered or directly connected
the output buffer is provided with skew control as well as tristate control
XC3000 IOB can sink or source 4 mA of current
XC4000 IOB can sink 12 mA or source 2mA

12. Programmable Interconnects
It consists of two layers of metal segments, programmable interconnect points (PIPs) and switch boxes.
PIP consists of a pass transistor that is controlled by a RAM cell. Dropping a ‘1’ into the cell establishes a connection between two points.
Three kinds of resources: long lines, short lines and general purpose interconnects

13. Programmable Interconnects contd..
Long lines: vertical and horizontal long lines run the entire height and width of the interconnect area. They are used to carry high-fanout signals or signals that need to travel long distance with low skew. The horizontal long lines can be connected to the tristate buffers. This allows the formation of buses, multiplexers and wired AND functions.
Short lines: for connecting adjacent CLBs and IOBs; used for short distance and low-delay communication.

14. Programmable Interconnects contd..
General purpose interconnect consists of a network of switching matrices and wire segments to facilitate general network branching and routing. In XC3000 series it consists of 5 horizontal and 5 vertical lines located between the rows and columns of CLBs. At the intersections there is a switch box called a switching matrix.
A switching matrix can establish connections in twenty different ways (4 or 5 or 6).

15. XC3000 Interconnects

16. Possible switch box connectivities

17. Actel: ACT1 Logic module
OHP fig.

18. Homework: What is the FPGA used in XSA50 board?
Describe its architecture, logic capabilities and
available resources for the user.
Due date: Sept. 22, 2003.