1. RECONFIGURABLE PROCESSING AND AVIONICS SYSTEMS
RUSS DUREN
DEPARTMENT OF ENGINEERING
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2. RECONFIGURABLE COMPUTING
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3. WHAT IS RECONFIGURABLE COMPUTING?
STANDARD COMPUTERS PERFORM DIFFERENT TASKS BY CHANGING THE PROGRAM THAT THE COMPUTER EXECUTES
RECONFIGURABLE COMPUTERS ARE PROGRAMMED BY CHANGING THE HARDWARE THAT EXECUTES THE PROGRAM
TYPICALLY RECONFIGURABLE COMPUTERS DO BOTH
STANDARD PROGRAMS ARE EXECUTED BY A STANDARD PROCESSOR
RECONFIGURABLE HARDWARE IS USED TO ACCELERATE CRITICAL PORTIONS OF THE CODE
RECONFIGURABLE HARDWARE IS IMPLEMENTED USING FIELD PROGRAMMABLE GATE ARRAYS (FPGAs)
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4. XILINX FIELD PROGRAMMABLE GATE ARRAYS
I/O Blocks (IOBs)
Programmable
Interconnect
Configurable
Logic Blocks (CLBs)
Special Purpose
Resources
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5. CONFIGURABLE LOGIC BLOCKS (CLBs)
BASIC RESOURCE UNIT IS THE SLICE
1 CLB CONTAINS 4 LOGIC CELLS
SLICE = 4-INPUT LOOK-UP TABLE (LUT) + D FLIP-FLOP
LUT CAPACITY LIMITED BY NUMBER OF INPUTS, NOT COMPLEXITY OF FUNCTION
LUTS CAN BE USED AS LOGIC, RAM, OR ROM
LUT FF
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6. Signed Multiply Performance
ADDITIONAL RESOURCES
INPUT/OUTPUT BLOCKS (IOBS)
PROGRAMMABLE INTERCONNECT
DELAY-LOCKED LOOPS (DLLS)
BLOCK RAM
FAST CARRY LOGIC
MULTIPLIERS
XC2V6000 VIRTEX II FPGA
33,792 SLICES
2,592 Kbits of BLOCK RAM
bit MULTIPLIERS
AT 140 MHz > 25 BILLION MULTIPLIES/SEC
18 Bit
36 Bit
8 x 8
210MHz
4 x 4
255MHz
12 x 12
170MHz
18 x 18
140MHz
Signed Multiply Performance
Preliminary V1.60 Speeds File
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7. PROCESSING SPEED IMPROVEMENTS
RECONFIGURABLE COMPUTERS USE FPGAS TO INCREASE PROCESSING SPEED BY:
USING CUSTOM HARDWARE TO COMPUTE RESULTS QUICKLY
USING PARALLEL CIRCUITRY TO COMPUTE MULTIPLE ANSWERS SIMULTANEOUSLY
USING PIPELINING TO INCREASE THROUGHPUT
ASSEMBLY LINE COMPUTATIONS
LATENCY
THROUGHPUT
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8. Microprocessor Chassis
SRC-6E
Microprocessor Chassis
MAP Chassis
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9. SRC-6E mP Chassis mP Chassis MAP Chassis Duren 9 P3 mP P3 mP P3 mP
(1000 MHz)
P3 mP
(1000 MHz)
P3 mP
(1000 MHz)
P3 mP
(1000 MHz)
800*
800*
8000
8000
MAP Chassis
Cache
Cache
Cache
Cache
800
Controller
Controller
800
MIOC
MIOC
4800
(6 x 800)
4800
(6 x 800)
PCI-X
Slots
SNAP
On-Board
Memory
(24 MB)
On-Board
Memory
(24 MB)
SNAP
PCI-X
Slots
Memory
(1.5 GB)
Memory
(1.5 GB)
4800
(6 x 800)
4800
(6 x 800)
User
Logic
User
Logic
User
Logic
User
Logic
2400
2400
* Peak Theoretical
315 MB/s Write
195 MB/s Read
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10. MAP Dual Processor Chain Port Board 18in x 13in Duren 10 Chain Port
Control Logic
DMA engine
Controls User Logic
User Logic
2 Virtex II - 6M gates each
100-MHz clock
Chain Port
MAP/SNAP
Cable
Connectors
On-Board Memory
6 dual-ported memory banks
24M bytes
64b data paths
Board
18in x 13in
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Chain Port

11. SRC-6E PROGRAMMING ENVIRONMENT
PENTIUM PROCESSORS
LINUX OPERATING SYSTEM IS THE MAIN USER INTERFACE
C AND FORTRAN COMPILERS FOR CODE DEVELOPMENT
INTEL AND GNU COMPILERS SUPPORTED
FPGAS
SRC-6E CUSTOM COMPILER CONVERTS HLL TO FPGA CIRCUITRY
FPGA ROUTINES WRITTEN IN C OR FORTRAN
SOFTWARE GENERATES ONE EXECUTABLE RESULT
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12. HARDWARE COMPILER
SRC COMPILER TRANSLATES THE C SOURCE INTO PIPELINED FPGA CIRCUITRY
FPGAS ARE CLOCKED AT 100 MHz
ONCE THE PIPELINE IS FILLED (LATENCY) RESULTS ARE PRODUCED EVERY 10 NANOSECONDS
IMPLEMENTS PARALLEL CIRCUITRY FOR INDEPENDENT STATEMENTS A(n) = my_func(X(n),Y(n)) A(n+1) = my_func(X(n+1),Y(n+1)) A(n+2) = my_func(X(n+2),Y(n+2)) A(n+3) = my_func(X(n+3),Y(n+3))
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13. LIMITATIONS IMPOSED ON HLL ROUTINES
VERSION 1.3 SUPPORTS:
DATA TYPES: 32-BIT (INT) AND 64-BIT (LONG LONG)
ADD, SUBTRACT, MULTIPLY
DIVISION (32-BIT ONLY)
RELATIONAL OPERATORS (==, !=, <, >, <=, >=)
BITWISE OPERATORS AND SHIFTS (&, |, !, <<, >>)
LOGICAL OPERATORS (&&, !, ||)
SQRT() (32BIT ONLY)
SOME RESTRICTIONS ON VARIABLE ACCESS AND CONTROL STATEMENTS
NOT PARTICULARLY LIMITING, BUT MUST BE CONSIDERED
EXAMPLE: NUMBER OF DATA WORDS TRANSFERRED MUST BE MULTIPLE OF 4
FUTURE VERSIONS OF THE COMPILER WILL SUPPORT MORE OPERATIONS AND DATA TYPES AND RELAX RESTRICTIONS
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14. RECONFIGURABLE RESEARCH TOPICS
APPLICATION DEVELOPMENT
FOR SRC-6E
FOR MULTIPLE FPGAS
PLATFORM COMPARISON
SRC, STARBRIDGE, WILDFIRE, NASA CLUSTER WITH FPGA NODES
ALGORITHM CLASSIFICATION
WHAT ALGORITHMS ARE BEST SUITED TO FPGA?
MATCHING ALGORITHMS TO ARCHITECTURES AND VICE VERSA
COMBINING ADAPTABLE HARDWARE WITH ADAPTABLE ALGORITHMS
NEURAL NETWORKS, GENETIC ALGORITHMS
DESIGN OF A CUSTOM RECONFIGURABLE PLATFORM
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15. AVIONICS SYSTEMS
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17. Federated Avionics System
HUD
MPD
KEYPAD
HOTAS
DISPLAY
CONTROLLER
SMS
STORES
MISSION
COMPUTER 1
INS/GPS
RADAR/
SENSORS
COMMS
MIL-STD-1553
Data Bus
MISSION
COMPUTER 2
FLIGHT
CONTROLS EW
SYSTEMS
DATA
LINK
Federated Avionics System
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18. AVIONICS RESEARCH TOPICS
DATA COMPRESSION ROUTINES FOR REAL-TIME, EMBEDDED, DEMAND-OPERATED SYSTEMS
SURVEY OF DATA TYPES AND TRANSMISSION RATES
SELECTION OF POTENTIAL COMPRESSION ROUTINES
ANALYSIS OF POTENTIAL BANDWIDTH SAVINGS
REAL-TIME SYSTEM ANALYSIS AND MODELING
EMERGING TOOLS FOR AVIONICS ARCHITECTURE MODELING AND ANALYSIS
SYSTEM OF SYSTEMS RESEARCH: HOW TO TAKE ADVANTAGE OF NETWORKED SYSTEMS
EXAMPLE: COMBAT ID - TARGET DETECTION, IDENTIFICATION, TRACKING, ELIMINATION OF MULTIPLE REPORTS
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19. RECONFIGURABLE AVIONICS SYSTEMS
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20. RECONFIGURABLE SATELLITE AVIONICS
NAVAL POSTGRADUATE SCHOOL CFTP PROGRAM
LAUNCHES SEPTEMBER 2006
PC-104 IBM PERSONAL COMPUTER
CUSTOM RECONFIGURABLE PROCESSOR BOARD
DEMONSTRATE COMMERCIAL, OFF-THE-SHELF FPGA TECHNOLOGY APPLIED TO SPACECRAFT ARCHITECTURE AS A MEANS OF
DECREASING DEVELOPMENT TIME
DECREASING COSTS
INCREASING FLEXIBILITY AND RELIABILITY
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21. Configurable Fault Tolerant Processor
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22. NPS Configurable Fault Tolerant Processor (CFTP)
EDAC
voter
memory
I/O
Status
TRIPLE-REDUNDANT, FAULT-TOLERANT RECONFIGURABLE SYSTEM-ON-A-CHIP (SOC)
DESIGN TO MITIGATE BIT ERRORS IN COMPUTATION BY DETECTING ERRORS AND CORRECTING THEM THROUGH VOTING LOGIC
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23. RECONFIGURABLE SPACE AVIONICS
RESEARCH OPPORTUNITIES
FAILURE ANALYSIS ON CURRENT DESIGN
ADDITIONAL EXPERIMENTS FOR RECONFIGURABLE BOARD
ERROR DETECTION
ERROR CORRECTION
FAULT TOLERANT CIRCUITS
PARTIAL FPGA RECONFIGURATION
TECHNIQUES FOR REMOTE DEBUGGING OF HARDWARE
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