1. CPE 528: Session #12
Department of Electrical and Computer Engineering University of Alabama in Huntsville

2. Introduction Actel Logic Modules Xilinx LCA Altera FLEX, Altera MAX
Outline
Introduction
Actel Logic Modules
Xilinx LCA
Altera FLEX, Altera MAX
Power Dissipation
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3. Basic internal structure
Introduction
Basic internal structure
PLB – Programmable Logic Blocks
PI – Programmable Interconnect
Types of basic logic cells
(1) multiplexer based
(2) look-up table based, and
(3) programmable array logic
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4. Actel ACT basic logic cell – Logic Module
Actel ACT 1 uses just one type of Logic Module
Actel ACT 2 and 3 use two different types of Logic Modules
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5. ACTEL Act 1 Logic Module
(a) Organization of the basic logic cells. (b) The ACT 1 Logic Module. (c) An implementation using pass transistors (without any buffering). (d) An example logic macro. (Source: Actel.)
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6. Shannon Expansion Theorem
Expansion F = F · 1 = F · (A + A’)= F · A + F · A‘
Example: expand F with respect to A F = A' · B + A · B · C' + A' · B' · C = A · (B · C') + A' · (B + B' · C)
cofactor F wrt A = B · C‘, cofactor F wrt A’ = B + B' · C
F with respect to B F = B · (A' + A · C') + B' · (A' · C)
We can continue to expand a function until we reach the canonical form – a unique representation that uses only minterms
minterm is a product term that contains all the variables of F
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7. An Example Implementation
F = (A · B) + (B' · C) + D = (A · B) + (B' · C) + [D ·(B + B’)] = B·(A+D) + B’·(C+D) = B·F2 + B’·F1
F2 = A + D = A + D·(A + A’) = A + A’·D = A·1 + A’·D
F1 = C + D = C + D·(C + C’) = C + C’·D = C·1 + C’·D
Implementation
A0 = D, A1 = 1, SA = C (F1)
B0 = D, B1 = 1, SB = A (F2)
S0 = 0, S1 = B
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8. Multiplexer Logic as Function Generators
Logic functions of 2 variables
10 functions of these 16 can be implemented using just one 2:1 multiplexer (See Table 5.1 of the textbook)
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9. Multiplexer Logic as Function Generators (cont’d)
Useful functions
INV. The MUX acts as an inverter for one input only.
BUF. The MUX just passes one of the MUX inputs directly to the output.
AND. A two-input AND.
OR. A two-input OR.
AND1-1. A two-input AND gate with inverted input, equivalent to an NOR-11.
NOR1-1. A two-input NOR gate with inverted input, equivalent to an AND-11.
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10. Multiplexer Logic as Function Generators (cont’d)
Figure 5.3 The ACT1 logic module as a boolean function generator. (a) A 2:1 MUX viewed as a logic wheel. (b) The ACT1 logic module viewed as two function wheels.
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11. F = (A · B)’ = A’ + B' = A’ + B’·(A’ + A) = A’ + B’· A = 1·A’ + B’·A
An Example
F = NAND(A, B)
F = (A · B)’ = A’ + B' = A’ + B’·(A’ + A) = A’ + B’· A = 1·A’ + B’·A
Implementation
Wheel 1 => 1 (A0 = 1, A1 = 1, SA = 1)
Wheel 2 => B’ (B0 = 1, B1 = 0, SB = B)
MUX (1, B’, A) => S0 = A, S1 = 0
Note: We do not have to worry how to use Logic Modules to construct combinational logic functions – e.g., we use NAND2 gate symbol and software takes care of connecting the inputs in the right way to the Logic Module
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12. ACT 2 and ACT 3 Logic Modules
Figure 5.4 The ACT2 and ACT3 logic modules. (a) The C-module. (b) The ACT2 S-module. (c) The ACT3 S-module. (d) The equivalent circuit of the SE. (e) The SE configured as a positive edge-triggered D flip-flop.
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13. Timing Model and Critical Path
Exact delay values in Actel FPGAs can not be determined until interconnect delay is known – i.e., place and route are done
Critical path delay between registers is: tPD + tSUD + tCO
There is also a hold time for the flip-flops - tH
The combinational logic delay tPD is dependent on the logic function (which may take more than one LM) and the wiring delays
The flip-flop output delay tCO can also be influenced by the number of gates it drives (fanout)
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14. Max delays in CMOS occur when
Worst-case timing
Max delays in CMOS occur when
operating under minimum voltage
maximum temperature
slow-slow process conditions (process variation which results in slow p-channel and slow n-channel transistors)
Electronic Equipment classes
Commercial. VDD = 5 V ± 5 %, T A (ambient) = 0 to +70 °C.
Industrial. VDD = 5 V ± 10 %, T A (ambient) = –40 to +85 °C.
Military: VDD = 5 V ± 10 %, T C (case) = –55 to +125 °C.
Military: Standard MIL-STD-883C Class B.
Military extended: Unmanned spacecraft.
Tj – junction temperature => temperature of the transistors on the chip
to calculate this we need power dissipated and thermal properties of the package
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15. Xilinx LCA
Xilinix LCA (Logic Cell Array) Configurable Logic Blocks (CLBs)
bigger and more complex than the Actel cells => coarse-grain architecture
XC3000 CLB inputs
five logic inputs (A-E)
common clock input (K)
asynchronous direct-reset input (RD)
enable clock (EC)
XC3000 CLB outputs
X, Y
Using programmable MUXes connected to the SRAM programming cells we can independently connect each of the two CLB outputs to the outputs of flip-flops (QX, QY) or to the output of the combinational logic (F, G)
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16. XC3000 CLB
Figure 5.6 The Xilinx XC3000 CLB (configurable logic block).
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17. XC3000 CLB (cont’d) LUT – Look-Up Table
32-bit LUT stored in 32 bits of SRAM
Suppose we need to implement the function F, F = A·B·C·D·E
set the content of LUT cell number 31 to 1
clear the content of all other LUT cells (0 – 30)
apply the input variables as an address to the SRAM
only when ABCDE = ‘11111’ the output F will be ‘1’
CLB propagation delay is fixed, equal to LUT access time and does not depend on the function implemented
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18. XC3000 CLB (cont’d) Combinational block inputs/outputs Using LUT
CLB inputs (A-E)
flip-flop outputs (QX, QY)
outputs from the LUT (F, G)
Using LUT
use five of seven inputs with the entire 32-bit LUT => CLB outputs F and G are identical
split the 32-bit LUT in half to implement two functions (outputs F and G) of four variables each
we can choose four input variables (A-E, QX, QY)
we have to choose two from the five CLB inputs (A-E)
split the 32-bit LUT in half, using one of seven input variables as a select input for a 2:1 MUX that switches between F and G
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19. XC4000 Logic Block Two four-input LUTs that feed a three-input LUT
Special fast carry logic hard-wired between CLBs
MUX control logic maps four control inputs C1-C4 into the four inputs:
LUT input (H1)
direct in (DIN)
enable clock (EC)
set/reset control for flip-flops (S/R)
Control inputs C1-C4 can also be used to control the use of the F’ and G’ LUTs as 32 bits of SRAM
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20. XC4000 Logic Block
Figure 5.7 The Xilinx XC4000 CLB (configurable logic block).
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21. XC5200 Logic Block
Basic Cell is called a Logic Cell (LC) and is similar to, but simpler than, CLBs in other Xilinx families
Term CLB is used here to mean a group of 4 LCs (LC0-LC3)
Figure 5.8 The Xilinx XC5200 LC (logic cell) and CLB (configurable logic block).
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22. Using LUTs to implement combinational logic
Xilinx CLB Analysis
Using LUTs to implement combinational logic
Disadvantage: an inverter is as slow as a five input NAND
Advantage: simplifies timing
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23. Altera FLEX (8000)
Basic Cell is called a Logic Element (LE) and resembles the Xilinx XC5200 LC architecture
Altera FLEX uses the same SRAM programming technology as Xilinx
Figure 5.10 The Altera FLEX architecture. (a) Chip floorplan. (b) LAB (Logic Array Block). (c) Details of the LE (logic element).
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24. Two-level logic circuit (sum of products)
Altera MAX
Two-level logic circuit (sum of products)
Using regular structure
vector of buffers
vector of AND gates
OR gates
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25. (a) Two-level logic circuit (sum of products)
Altera MAX (cont’d)
(a) Two-level logic circuit (sum of products)
(c) Programmable Array Logic (PAL)
Horizontal line: product term line (bit line)
Vertical line: word line
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26. Altera MAX (cont’d)
Programmed EPROM transistor has no effect on the product-term line
Unprogrammed EPROM acts as a pull-down tran.
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27. Registered PAL
Figure 5.12 A registered PAL with I inputs, j product terms, and k macrocells.
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28. Logic Expanders
A logic expander is an output line of the AND array that feeds back as an input to the array itself
Logic expanders can help implement functions that require more product terms than are available in a simple PAL
Consider implementing this function in in a three-wide OR array: F = A’ · C · D + B’ · C · D + A · B + B · C’
This can be rewritten as a “sum of (products of products): F = (A’ + B’) · C · D + (A + C’) · B F = (A · B)’ (C · D) + (A’ · C)’ · B
Logic expanders can be used to form the expander terms (A · B)’ and (A’ · C)’
Logic expanders require an extra pass through the AND array, increasing delay
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29. Logic Expander Implementation
Figure 5.13 Expander logic and programmable inversion.
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30. Logic Expanders (cont’d)
Programmable inversion
programming one input of the XOR gate at the macrocell output allows you to choose whether or not to invert the output
this can reduce the required number of product terms
Figure 5.14 Use of programmed inversion to simplify logic. (a) The function F = A·B’+ A·C’+ A·D’+ A’·C·D requires four product terms to implement while (b) the complement F’ = A·B·C·D+ A’·D’+ A’·C’ requires only three product terms.
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31. Altera MAX architecture
Macrocell features:
Wide, programmable AND array
Narrow, fixed OR array
Logic Expanders
Programmable inversion
Figure 5.15 The Altera MAX architecture. (a) Organization of logic and interconnect. (b) A MAX family LAB (Logic Array Block). (c) A MAX family macrocell.
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32. Timing Model Direct path through the logic array and register
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33. Timing Model
Using parallel expander
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34. Using a shared expander (two passes through the logic array)
Timing Model
Using a shared expander (two passes through the logic array)
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35. Power Dissipation in Complex PLDs
AND arrays consume static power
AND arrays in any PLD built using EPROM or EEPROM transistors use a passive pull-up (a resistor or current source)
Altera uses a switch called Turbo Bit to control the current in the programmable-AND array in each macrocell
MAX 7000 static current
1.4 mA – 2.2 mA per macrocell in high-power mode
0.6 mA – 0.8 mA per macrocell in low-power mode
MAX 9000 static current
0.6 mA – 0.8 mA per macrocell in high-power mode
0.3 mA per macrocell in low-power mode
MAX 9000: 16 macrocells in LAB, 35 LABs => static power dissipation in low-power mode = 840mW
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