1. Counters as State Machines
Lecture L9.1
Section 9.1

2. Counters as State Machines
Divide by 8 Counter
A Divide-by-16 Counter with Count Enable

3. Divide-by-8 Counter s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
CLK D Q !Q Q0
Q0.D Q1 Q2
Q1.D
Q2.D

4. Divide-by-8 Counter s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1
Q1 Q0 s s s s s s s s
State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 1 1 1 1
Q2.D
Q2.D = !Q2 & Q1 & Q0
# Q2 & !Q1
# Q2 & !Q0

5. Divide-by-8 Counter s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1
Q1 Q0 s s s s s s s s
State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 1 1 1 1
Q1.D
Q1.D = !Q1 & Q0
# Q1 & !Q0

6. Divide-by-8 Counter s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1
Q1 Q0 s s s s s s s s
State Q2 Q1 Q0 Q2.D Q1.D Q0.D 00 01 11 10 Q2 1 1 1 1 1
Q0.D
Q0.D = ! Q0

7. Divide-by-8 Counter
A state machine for a divide by 8 counter

8. Divide-by-8 Counter s0 0 0 0 0 0 1 s1 0 0 1 0 1 0 s2 0 1 0 0 1 1
State Q2 Q1 Q0 Q2.D Q1.D Q0.D
A state-transition table

9. Divide-by-8 Counter
A Divide by 8 counter
Circuit using D Flip-flops

10. div8cnts.abl MODULE div8cnts
TITLE 'Divide by 8 Counter using State Machine'
DECLARATIONS
hex7seg interface([D3..D0] -> [a,b,c,d,e,f,g]);
d7R FUNCTIONAL_BLOCK hex7seg;
" INPUT PINS "
CLK PIN 12; " 1 Hz clock (jumper)
clear PIN 11; " switch 1
" OUTPUT PINS "
Q2..Q0 PIN 41,43,44 ISTYPE 'reg'; " LED
Q = [Q2..Q0]; " 3-bit output vector
[a,b,c,d,e,f,g] PIN 15,18,23,21,19,14,17 ISTYPE 'com';
" Rightmost (units) 7-segment LED display

11. div8cnts.abl (cont.) Define the states; Associate a variable name
" Definitions
QSTATE = [Q2,Q1,Q0];
s0 = [0,0,0];
s1 = [0,0,1];
s2 = [0,1,0];
s3 = [0,1,1];
s4 = [1,0,0];
s5 = [1,0,1];
s6 = [1,1,0];
s7 = [1,1,1];
state_diagram QSTATE
state s0: GOTO s1;
state s1: GOTO s2;
state s2: GOTO s3;
state s3: GOTO s4;
state s4: GOTO s5;
state s5: GOTO s6;
state s6: GOTO s7;
state s7: GOTO s0;
Define the states;
Associate a variable name
With a numerical representation
Define the transitions
between the states

12. div8cnts.abl (cont.) Connect the clock Connect the 7-segment display
EQUATIONS
Q.AR = clear;
Q.C = CLK;
[a,b,c,d,e,f,g] = d7R.[a,b,c,d,e,f,g];
d7R.[D2..D0] = Q;
d7R.D3 = 0;
Connect the clock
Connect the 7-segment display

13. div8cnts.abl (cont.) test_vectors([CLK, clear] -> Q)
END div8cnts

14. Counters as State Machines
Divide by 8 Counter
A Divide-by-16 Counter with Count Enable

15. A Divide-by-16 Counter with Count Enable
count = 1 Counter counts
count = 0 Counter stops counting
Cout = 1 if [Q3..Q0] = [1,1,1,1] and count = 1

16. State Diagram for a Divide-by-16 Counter with Count Enable

17. div16cnt.abl MODULE div16cnt
interface ([CLK,clear,count] -> [Q3,Q2,Q1,Q0,Cout]);
TITLE 'Divide by 16 (4-bit) Counter using State Machine'
DECLARATIONS
" INPUT PINS "
CLK PIN ; " clock input
clear PIN ; " asynchronous clear
count PIN ; " count enable
" OUTPUT PINS "
Q3..Q0 PIN ISTYPE 'reg';
Q = [Q3..Q0]; " 4-bit output vector
Cout PIN ISTYPE 'com'; " Carry out

18. div16cnt.abl (cont.) " Definitions QSTATE = [Q3,Q2,Q1,Q0];

19. div16cnt.abl (cont.) Use If..Then statements to implement the count
state_diagram QSTATE
state s0: if count then s1
else s0;
state s1: if count then s2;
else s1;
state s2: if count then s3;
else s2;
state s3: if count then s4;
else s3;
state s4: if count then s5;
else s4;
state s5: if count then s6;
else s5;
state s6: if count then s7;
else s6;
state s7: if count then s8;
else s7;
Use If..Then statements to
implement the count

20. div16cnt.abl (cont.) state s8: if count then s9 else s8;

21. div16cnt.abl (cont.) EQUATIONS Q.C = CLK; Q.AR = clear;
Q.C = CLK;
Q.AR = clear;
Cout = Q3 & Q2 & Q1 & Q0 & count;
END div16cnt

22. 8-Bit Counter