1. Introduction To Verilog-HDL
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

2. Department of Computer Science & Engg
Parameterized Design
module vector_and(z, a, b);
parameter cardinality = 1;
input [cardinality-1:0] a, b;
output [cardinality-1:0] z;
wire [cardinality-1:0] z = a & b;
endmodule
We override these parameters when we instantiate the module as:
module Four_and_gates(OutBus, InBusA, InBusB);
input [3:0] InBusA, InBusB; output[3:0] OutBus;
Vector_And #(4) My_And(OutBus, InBusA, InBusB);
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

3. Department of Computer Science & Engg
Parameterized Design
module vector_and(z, a, b);
parameter cardinality = 1;
input [cardinality-1:0] a, b;
output [cardinality-1:0] z;
wire [cardinality-1:0] z = a & b;
endmodule
We override these parameters when we instantiate the module as:
module Four_and_gates(OutBus, InBusA, InBusB);
input [3:0] InBusA, InBusB; output[3:0] OutBus;
Vector_And #(4) My_And(OutBus, InBusA, InBusB);
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

4. Department of Computer Science & Engg
Functions (cont’d)
Function Declaration and Invocation
Declaration syntax:
function <range_or_type> <func_name>;
<input declaration(s)>
<variable_declaration(s)>
begin // if more than one statement needed
<statements>
end // if begin used
endfunction
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

5. Function Examples Controllable Shifter
module shifter;
`define LEFT_SHIFT 'b0
`define RIGHT_SHIFT 1'b1
reg [31:0] addr, left_addr, right_addr;
reg control;
initial
begin …
end
left_addr =shift(addr, `LEFT_SHIFT);
right_addr =shift(addr,`RIGHT_SHIFT);
function [31:0]shift;
input [31:0] address;
input control;
begin
shift = (control==`LEFT_SHIFT) ?(address<<1) : (address>>1);
end
endfunction
endmodule
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

6. How Are Simulators Used?
Testbench generates stimulus and checks response
Coupled to model of the system
Pair is run simultaneously
Testbench
System Model
Stimulus
Response
Result checker
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

7. Structure of Testbench
module <module name>
<reg and wire declarations>
<Instantiate the Verilog design>
<generate stimulus using initial and always
keywords>
<produce the outputs using $monitor for
verification>
endmodule
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

8. Looking back at our multiplexer
“Dataflow” Descriptions of Logic
//Dataflow description of mux
module mux2 (in0, in1, select, out);
input in0,in1,select;
output out;
assign out = (~select & in0)
| (select & in1);
endmodule // mux2
Alternative:
assign out = select ? in1 : in0;
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

9. TestBench of the Multiplexer
module testmux;
reg a, b, s;
wire f;
reg expected;
mux2 myMux (.select(s), .in0(a), .in1(b), .out(f));
initial
begin
s=0; a=0; b=1; expected=0;
#10 a=1; b=0; expected=1;
#10 s=1; a=0; b=1; expected=1;
end
$monitor(
"select=%b in0=%b in1=%b out=%b, expected out=%b time=%d",
s, a, b, f, expected, $time);
endmodule // testmux
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

10. How to write synthesizable codes
The following cannot be translated into hardware( non - synthesizable):
Initial blocks
Used to set up initial state or describe finite testbench stimuli
Don’t have obvious hardware component
Delays
May be in the Verilog source, but are simply ignored
In short, write codes with a hardware in your mind. In other words do not depend too much upon the tool to decide upon the resultant hardware.
Finally, remember that you are a better designer than the tool.
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

11. Typical Combinational Circuits
Write a Verilog description for a 2 to 4 decoder
(a) Using behavioral modeling
module decoder ( Y3, Y2, Y1, Y0, A, B, en);
// define inputs and outputs
output Y3, Y2, Y1, Y0;
input A, B;
input en;
reg Y3, Y2, Y1, Y0;
(A or B or en)
begin
if (en == 1)
case ( {A,B} )
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

12. Department of Computer Science & Engg
2 to 4 decoder contd.
2’b00: {Y3, Y2, Y1, Y0} = 4’b0001;
2’b01: {Y3, Y2, Y1, Y0} = 4’b0010;
2’b10: {Y3, Y2, Y1, Y0} = 4’b0100;
2’b11: {Y3, Y2, Y1, Y0} = 4’b0001;
default : {Y3, Y2, Y1, Y0} = 4’b1xxxx;
endcase
end
if (en == 0)
{Y3, Y2, Y1, Y0} = 4’b0000;
endmodule
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

13. Department of Computer Science & Engg
2 to 4 decoder contd.
(b) Using dataflow modeling
// file name : decoder.v
module decoder (E, X, Y, Z0, Z1, Z2, Z3);
output Z0, Z1, Z2, Z3;
input E, X, Y;
assign Z0 = E & ~X & ~Y;
assign Z1 = E & ~X & Y;
assign Z2 = E & X & ~Y;
assign Z3 = E & X & Y;
endmodule
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

14. Department of Computer Science & Engg
2 to 4 decoder contd.
(b) Using structural modeling modeling
// file name : decoder.v
module decoder (D, E, X, Y);
output [0:3] D;
input E, X, Y;
wire [0:3] D; // output D must be declared as wire
wire X1, Y1;
not (X1, X);
not (Y1, Y);
and (D[0], X1, Y1, E);
and (D[1], X1, Y, E);
and (D[2], X, Y1, E);
and (D[3], X, Y, E);
endmodule
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

15. Department of Computer Science & Engg
Verilog for Full Adder
// Full Adder using 3 to 8 decoder and 2 four input AND gates
module fulladder (C, S, X, Y, Z);
output C, S;
input X, Y, Z;
wire [7:0] decoder_out;
// 3 to 8 decoder enabled with bits to be added as inputs
decoder decoder 74138_0 (decoder_out [7:0], 1’b1, 1’b0, 1’b0, X, Y, Z);
// use 4 input AND gates to find Sum and Carry
AND4_0 (S, decoder_out[0], decoder_out[3], decoder_out[5], decoder_out[6]);
AND4_0 (S, decoder_out[0], decoder_out[1], decoder_out[2], decoder_out[4]);
endmodule
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

16. Testbench for Full Adder
// Full Adder using 3 to 8 decoder and 2 four input AND gates
module fulladdertest (C, S, X, Y, Z);
wire C, S;
reg X, Y, Z;
wire [7:0] decoder_out;
fulladder fulladder_0 (C, S, X, Y, Z);
initial
$monitor(“Time = %d, X=%b, Y=%b, Z=%b, S=%b, C=%b”,
$time, X, Y, Z, S, C);
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

17. Testbench for Full Adder
initial
begin
#0 X = 1’b0; Y = 1’b0; Z = 1’b0;
#0 X = 1’b0; Y = 1’b0; Z = 1’b1;
#0 X = 1’b0; Y = 1’b1; Z = 1’b0;
#0 X = 1’b0; Y = 1’b1; Z = 1’b1;
#0 X = 1’b1; Y = 1’b0; Z = 1’b0;
#0 X = 1’b1; Y = 1’b0; Z = 1’b1;
#0 X = 1’b1; Y = 1’b1; Z = 1’b0;
#0 X = 1’b1; Y = 1’b1; Z = 1’b1;
end
endmodule
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur

18. Department of Computer Science & Engg
Verilog Assignments
Write Verilog code for a 4 to 1 multiplexer using
(a) using structural modeling
(b) conditional operator
Write Verilog code for 1 2-bit unsigned comparator
Write Verilog code for a 4-bit ripple carry adder using
(a) behavioral modeling
(b) hierarchical modeling
Write Verilog code fro BCD to seven-segment code converter for driving a common –cathode display for displaying the decimal digits 0 to 9.
16 November 2018
Department of Computer Science & Engg
IIT Kharagpur