1. Graded Quiz #5 Oct. 4, 2017 Clicker [AB]
Covers:
Module 2.A and 2.B

2. The operation taking place between time 0 and time 100 is a:
(A) Write
(B) Read
(C) Not enough information to tell
The operation taking place between time 0 and time 100 is a:
(A) Write
(B) Read 
(C) Not enough information to tell

3. Assuming the cycle before 0 was a write operation, the minimum information I need to derive all the information currently on this diagram is:
(A) CPU timing parameters
(B) SRAM timing parameters
(C) SRAM timing parameters + glue logic delays
(D) CPU timing parameters + glue logic delays
(E) CPU + SRAM + glue logic needed
Assuming the cycle before 0 was a write operation, the minimum information I need to derive all the information currently on this diagram is:
(A) CPU timing parameters
(B) SRAM timing parameters
(C) SRAM timing parameters + glue logic delays
(D) CPU timing parameters + glue logic delays 
(E) CPU + SRAM + glue logic needed

4. Assuming the cycle before 0 was a read operation, the minimum information I need to derive all the information currently on this diagram is:
(A) CPU timing parameters
(B) SRAM timing parameters
(C) SRAM timing parameters + glue logic delays
(D) CPU timing parameters + glue logic delays
(E) CPU + SRAM + glue logic needed
Assuming the cycle before 0 was a read operation, the minimum information I need to derive all the information currently on this diagram is:
(A) CPU timing parameters
(B) SRAM timing parameters
(C) SRAM timing parameters + glue logic delays
(D) CPU timing parameters + glue logic delays
(E) CPU + SRAM + glue logic needed 

5. The address generation delay time (tAD) for this CPU is:
(A) 20ns
(B) 30ns
(C) 40ns
(D) 50ns
(E) Not enough information to tell
The address generation delay time (tAD) for this CPU is:
(A) 20ns
(B) 30ns
(C) 40ns
(C) 50ns 
(C) Not enough information to tell

6. The glue logic delays on this diagram are:
(A) CE’=20ns, OE’=20ns
(B) CE’=20ns, OE’=10ns
(C) CE’=10ns, OE’=10ns
(D) CE’=30ns, OE’=10ns
(E) Not enough information to tell
The glue logic delays on this diagram are:
(A) CE’=20ns, OE’=20ns
(B) CE’=20ns, OE’=10ns 
(C) CE’=10ns, OE’=10ns
(D) CE’=30ns, OE’=10ns
(E) Not enough information to tell

7. Given the following CPU + SRAM Parameters, what is the read margin?
SRAM tAA=30ns
SRAM tCE=10ns
SRAM tOE=10ns
CPU tRS=20ns
(A) 0ns
(B) 10ns
(C) 20ns
(D) 30ns
(E) None - setup time is violated
Given the following CPU + SRAM Parameters, what is the read margin?
SRAM tAA=30ns
SRAM tCE=10ns
SRAM tOE=10ns
CPU tRS=20ns
(A) 0ns 
(B) 10ns
(C) 20ns
(D) 30ns
(E) None - setup time is violated