1. Computer Science 210 Computer Organization
The von Neumann Architecture

2. John von Neumann ( )

3. Origins
Early 1940s – first electronic digital computers (Atanasoff, Eckert & Mauchly)
1945 – von Neumann writes draft report on EDVAC, first stored program computer
Memory
Processing unit
Control Unit

4. The von Neumann Model

5. Memory 2k by m array of bits Address of k bits Contents of m bits
Basic operations:
Load (read)
Store (write)
0000
0001
0010
0011
0100
0101
0110
1101
1110
1111 •

6. Interface to Memory MAR: Memory Address Register
MDR: Memory Data Register
To LOAD a value from a location (A):
Write the address (A) into the MAR.
Send a “read” signal to the memory.
Read the data from MDR.
To STORE a value (X) to a location (A):
Write the data (X) to the MDR.
Send a “write” signal to the memory.

7. Processing Unit ALU: Arithmetic and Logic Unit Registers:
Small set of temporary storage cells.
Store operands and results of processing units.
LC3 has 8 registers, R0..R7, 16 bits wide.
Word size: 16 bits

8. Control Unit
PC: Program Counter, contains address of the next instruction
IR: Instruction Register, contains the currently executing instruction
Read an instruction from memory
Decode the instruction, signaling other components to perform actions

9. From Logic to Data Path
The von Neumann components are implemented as a data path
Combinational logic – decoders, muxes, ALU
Sequential logic – finite state machine, latches, registers

10. The LC3 Data Path
Combinational
Logic
Storage
State Machine

11. State Machine (a.k.a. Finite Automaton, Finite State Automaton, Deterministic Finite-State Automaton, Deterministic Finite Automaton)
This example has two states (S1, S2) and two possible input values (0,1), but typical state machines will have more states.
The circle around S1 means that we accept the input sequence if we reach S1.
We can also represent it using a table:
Current State
Input Value
New State S1 S2 1

12. State Machine Example: File Access
Current State
Input Value (action)
New State
Closed
open(‘r’)
Ready to read
open(‘w’)
Ready write
read()
ERROR
write()
close()
Ready to write

13. Finish Chapter 4 The machine code execution cycle
For Friday
Finish Chapter 4
The machine code execution cycle