1. Information Storage and Spintronics 10
Atsufumi Hirohata
Department of Electronic Engineering
09:00 Tuesday, 30/October/2018 (J/Q 004)

2. Quick Review over the Last Lecture
Flash memory :
NAND-flash writing operation :
NOR-type
1 byte high-speed read-out
Low writing speed
Difficult to integrate
NAND-type
No 1 byte high-speed read-out
High writing speed
Ideal for integration
NAND-flash erasing operation :
Flash erase for a unit block ( 1 ~ 10 kbyte ) only ! *

3. 10 Dynamic Random Access Memory
Memory cell
Architecture
Data storage
Read-out
Refresh
Further integration

4. Flash Memory vs DRAM Comparisons between flash memory and DRAM :
Tunnel barrier
Floating gate
Principles
Transistor
Transistor
Condenser
Electron charges
are stored in the On On
Electrons are stored at the floating gate.
condenser.
Writing operation
Leakage from
the condenser.
Electrons cannot
tunnel through the
barriers.
Data volatility * 4

5. Storage and Working Memories
Current major memories for storage and work : * 5

6. Dynamic Random Access Memory (DRAM)
In a computer, data is transferred from a HDD to a Dynamic Random Access Memory :
Data stored in a capacitor.
 Electric charge needs to be refreshed.
 DRAM requires large power consumption. * 6

7. DRAM Packages DRAM design : DRAM packages : Dual in-line package (DIP)
Single in-line pin package (SIPP)
Single in-line memory module (SIMM) 30-pin
SIMM 72-pin
Dual in-line memory module (DIMM) 168-pin
Double data rate (DDR) DIMM 184-pin * 7

8. Memory Cell Development
DRAM memory cells : * 8

9. Memory Storage
1 DRAM cell consists of 1 capacitor + 1 switching FET (1C1T) :
“1”-state :
1 V
Floating
capacitor
0 V
OFF
2 V
Capacitor
“0”-state :
1 V
0 V
OFF
0 V * 9

10. Memory Read-Out Read-out operation of 1C1T : Word line (3.6 V)
“1”-data :
1 V + ΔV = 2 V
3.6 V
Data
rewrite ON
2 V = 1 V + ΔV
“0”-data :
1 V – ΔV = 0 V
3.6 V ON
0 V = 1 V – ΔV * ** 10

11. Memory Refresh Refresh operation of 1C1T :* 11

12. DRAM Architecture
DRAM architecture :: * 12

13. Data Access Speed Addressing a cell : Raw address strobe (RAS)
Column address strobe (CAS)
Page mode enables to address different columns in the same raw.
→ Fast page mode
→ Extended data out (EDO)
→ Synchronous DRAM
PC-100 : 100 MHz cycles
Access time
60 ~ 80 ns
Cycle time
40 ~ 50 ns
Raw 1
Col. 1
Col. 2
Col. 3
Data1
Data2
Data3
Access time
50 ~ 70 ns
Cycle time
20 ~ 30 ns
Raw 1
Col. 1
Col. 2
Col. 3
Col. 4
Data1
Data2
Data3 * 13

14. Synchronous DRAM (SDRAM)
SDRAM access diagram : * 14

15. DRAM Trends DRAM follows Moore’s law (160 % / yr.) :* 15

16. DRAM Design Developments
Storage node shapes : * 16

17. Fin-Type DRAM Designs
Various manufacturers developed different designs : * 17

18. Cells, Pages and Blocks Typical 10Gbit DRAM with high-k materials :* 18

19. For Higher Recording Density ...
Conventional DRAM cell :
Next-generation DRAM cell :
Word line
Word line
Bit line
Bit line
Capacitor
Capacitor
1-cell size
1-cell size
Capacitor
Source
Word line
Insulator for gating
Channel
Drain
Bit line * 19

20. DRAM Market Market dominated by 3 major manufacturers :* 20

21. Super Pillar Transistor (SPT)
Universal transistor architecture for various memories : * 21

22. Memory Types Rewritable Volatile Dynamic DRAM Static SRAM Non-volatile
MRAM
FeRAM
PRAM
Read only
Non-volatile
Static
PROM
Mask ROM
Read majority
(Writable)
Non-volatile
Static
Flash
EPROM * 22

23. Major Memories * 23