1. ELEC 7770 Advanced VLSI Design Spring 2012 Clock Skew Problem
Vishwani D. Agrawal
James J. Danaher Professor
ECE Department, Auburn University
Auburn, AL 36849
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

2. ELEC 7770: Advanced VLSI Design (Agrawal)
Single Clock
FF A
Comb.
FF B
Data_in
Data_out
CKA
CKB CK
CKA
CKB
Single-cycle path delay
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

3. ELEC 7770: Advanced VLSI Design (Agrawal)
Multiple Clocks
FF A
Comb.
FF B
Data_in
Data_out
CKA
CKB
CKA
CKB
Multi-cycle path delay
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

4. ELEC 7770: Advanced VLSI Design (Agrawal)
Clock Skew
Skew is the time delay of clock signal at a flip-flop with respect to some time reference.
For a given layout each flip-flop has a skew, measured with respect to a common reference.
Skews of flip-flops separated by combinational paths affect the short-path and long-path constraints.
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

5. Skews for Single-Cycle Paths
Combinational
Block
Delay:
FFi
CKi
FFj
CKj
δ(i,j) ≤ d(i,j) ≤ Δ(i,j) xi xj
xi and xj are arrival times of clock edges
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

6. ELEC 7770: Advanced VLSI Design (Agrawal)
Delay Latch or D-Latch
SR-latch D CK Q Q
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

7. Setup and Hold Times of Latch
Signals are synchronized with respect to clock (CK).
Operation is level-sensitive:
CK = 1 allows data (D) to pass through
CK = 0 holds the value of Q, ignores data (D)
Setup time is the interval before the clock transition during which data (D) should be stable (not change). This will avoid any possible race condition.
Hold time is the interval after the clock transition during which data should not change. This will avoid data from latching incorrectly.
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

8. ELEC 7770: Advanced VLSI Design (Agrawal)
Latch Inputs tp 1 D
time Ts Th 1 CK
time Tr
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

9. Master-Slave D-Flip-Flop
Master latch
Slave latch D CK Q Q
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

10. Master-Slave D-Flip-Flop
Uses two level-sensitive clocked D-latches.
Transfers data (D) with one clock period delay.
Operation is edge-triggered:
Negative edge-triggered, CK = 1→0, Q = D (previous slide)
Positive edge-triggered, CK = 0→1, Q = D
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

11. Negative-Edge Triggered D-Flip-Flop
Clock period, Tck
Slave open
Master closed
Master open
Slave closed CK D
Triggering clock edge
Hold time Th
Setup time Ts
Data
stable
Data can change
Data can change
Time
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

12. Skews for Single-Cycle Paths
Combinational
Block
Delay:
FFi
CKi
FFj
CKj
δ(i,j) ≤ d(i,j) ≤ Δ(i,j) xi xj
xi and xj are arrival times of clock edges
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

13. Short-Path Constraint (Double-Clocking)
Tck
CKi si
intended
Not intended
CKj
Thj sj
δ(i,j)
si + δ(i,j) ≥ sj + Thj
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

14. Long-Path Constraint (Zero-Clocking)
Tck
CKi si
Not intended
intended
CKj sj
Tsj
Δ(i,j)
si + Δ(i,j) ≤ sj + Tck – Tsj
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

15. Maximum Clock Frequency
Linear program:
Objective function, Minimize Tck
Subject to constraints, for all flip-flop pairs (i,j),
(1) si + δ(i,j) ≥ sj + Thj short path
(2) si + Δ(i,j) ≤ sj + Tck – Tsj long path
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

16. Effects of Constraints
Short path:
Independent of clock
δ(i,j) ≥ sj – si + Thj
Long path:
Tck ≥ si – sj + Δ(i,j) + Tsj
Example: Shift register, δ(i,j) ≈ Δ(i,j) ≈ 0
si – sj ≥ Thj > 0 si > sj for correct operation
Tck ≥ si – sj + Tsj sj > si for maximum speed
Clock routed opposite to data
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

17. Shift Register Example
Delay ≈ 0
Delay ≈ 0
FFi
FFj
FFk
Delay = si sj sk CK Ri Rj Rk Ci Cj Ck
si – sj ≥ Thj for correct operation
Tck ≥ si – sj + Tsj for correct operation
Maximum clock speed, Tck = Thj + Tsj
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

18. ELEC 7770: Advanced VLSI Design (Agrawal)
Finding Clock Skews sk
FFi
FFj
FFk si CK Ri Rj Rk Ci Cj Ck sj
Use Elmore delay formula to calculate si, sj, sk.
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

19. Interconnect Delay: Elmore Delay Model
W. Elmore, “The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers,” J. Appl. Phys., vol. 19, no.1, pp , Jan Ri i Rj j Rk k CK Ci
Shared resistance:
Rii = Ri
Rij = Rji = Ri
Rik = Rki = Ri
Rjj = Ri + Rj
Rjk = Rkj = Ri + Rj
Rkk = Ri + Rj + Rk Cj Ck
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

20. Elmore Delay Calculation
Delay at nodes, sk = 0.69 (Ci × Rik + Cj × Rjk + Ck × Rkk )
= 0.69 [Ri Ci + (Ri + Rj) Cj + (Ri + Rj + Rk)Ck]
sj = 0.69 [Ri Ci + (Ri + Rj) (Cj + Ck)]
si = 0.69 [Ri (Ci + Cj + Ck)]
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

21. ELEC 7770: Advanced VLSI Design (Agrawal)
Example 1Ω i 1Ω j 1Ω k CK
1pF
1pF
1pF
si = 0.69 × 3 ps
sj = 0.69 × 5 ps
sk = 0.69 × 6 ps
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

22. Finding δ(I,j) and Δ(I,j)
Minimum delay
Maximum delay
, - A 1
, - H 3
9, 10 j
, -
0, 0 B 3
3, 3
4, 4 i E 1 G 2
6, 7
, - C 1
, - J 1
6, 8 F 1 k
, -
5, 5 D 2
, -
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

23. Maximum Clock Frequency for Tolerance ±q/2 in Skew
Linear program: Minimize Tck
Subject to: For all flip-flop pairs (i,j),
si + δ(i,j) ≥ sj + Thj + q
si + Δ(i,j) ≤ sj + Tck – Tsj – q
Where q is a constant
si are variables, simin ≤ si
Tck is a variable
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

24. Maximum Tolerance for Given Clock Frequency
Linear program: Maximize q
Subject to: For all flip-flop pairs (i,j),
si + δ(i,j) ≥ sj + Thj + q
si + Δ(i,j) ≤ sj + Tck – Tsj – q
Where Tck is a constant
si are variables, simin ≤ si
q is a variable
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

25. ELEC 7770: Advanced VLSI Design (Agrawal)
Tradeoffs
No solution because of
zero slack.
Increasing skew tolerance q
Increasing clock period Tck
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)

26. ELEC 7770: Advanced VLSI Design (Agrawal)
Clock Skew Problem
N. Maheshwari and S. S. Sapatnekar, Timing Analysis and Optimization of Sequential Circuits, Springer, 1999.
J. P. Fishburn, “Clock Skew Optimization,” IEEE Trans. Computers, vol. 39, no. 7, pp , July 1990.
Spring 2012, Feb
ELEC 7770: Advanced VLSI Design (Agrawal)