1. Lecturer: Huai-Yi Hsu (許槐益) Date: 2004.02.27
Digital IC Design Flow
Lecturer: Huai-Yi Hsu (許槐益)
Date:

2. Outline Introduction IC Design Flow Verilog History HDL concept
Digital IC Design Flow
Huai-Yi Hsu

3. Moore’s Law: Driving Technology Advances
Logic capacity doubles per IC at regular intervals (1965).
Logic capacity doubles per IC every 18 months (1975).
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Huai-Yi Hsu

4. Process Technology Evolution
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5. Chips Sizes Source: IBM and Dataquest
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Huai-Yi Hsu

6. Shrinking Product Cycles
Shrinking development turnaround times
Need for productivity increase (remember the “design gap”)
PCS: Personal Communication Services
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Huai-Yi Hsu

7. Design Productivity Crisis
Human factors may limit design more than technology.
Keys to solve the productivity crisis:
Design techniques: hierarchical design, SoC design (IP reuse, platform-based design), etc.
CAD: algorithms & methodology
Digital IC Design Flow
Huai-Yi Hsu

8. Increasing Processing Power
Very high performance circuits in today’s technologies.
Gate delays: ~27ps for a 2-input Nand in CU11
Operating frequencies: up to 500MHz for SoC/Asic, over 1GHz for custom designs
The increase in speed/performance of circuits allowed blocks to be reused without having to be redesigned and tuned for each application
Enhanced Design Tools and Techniques
Although not enough to close the “design gap”, tools are essential for the design of today’s high-performance chips
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Huai-Yi Hsu

9. IP-Based SoCs An Evolutionary Path
Early days
IP/Cores not really designed for reuse (no standard deliverables)
Multiple Interfaces, difficult to integrate
IPs evolved: parameterization, deliverables, verification, synthesizable
On-Chip bus standards began to appear (e.g, IBM, ARM)
Reusable IP + Common on-chip bus architectures
1998: max number of cores > 30 cores core content between 50% and 95%
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Huai-Yi Hsu

10. IP / Cores Soft Core Firm Core Hard Core
Delivered as RTL verilog or VHDL source code with synthesis script (i.e: clock generation logic)
Customers are responsible for synthesis, timing closure, and all front-end processing
Firm Core
Delivered as a netlist to be included in customer’s netlist (with don't touch attribute)
Possibly with placement information
Hard Core
Due to their complexity, they are provided as a blackbox (GL1/GDSII). Ex. Processors, analog cores, PLLs
Usually very tight timing constraints. Internal views not be alterable or visible to the customer
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Huai-Yi Hsu

11. Changes in the Nature of IC Design
(IEEE Spectrum Nov,1996)
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12. Chasing the Design Gap
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13. Evolution of Silicon Design
Source: “Surviving the SoC revolution – A Guide to Platform-based Design,” Henry Chang et al, Kluwer Academic Publishers, 1999
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14. Methodology – Analysis and Verification
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Huai-Yi Hsu

15. IC Design and Implementation
Idea
Design
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Huai-Yi Hsu

16. Design Flow Back End Front End Design Specification Pre-Synthesis
Sign-Off
Cell Placement, Scan
Chain & Clock Tree
Insertion, Cell Routing
Design Partition
Synthesize and Map Gate-Level Netlist
Verify Physical &
Electrical Design Rules
Design Entry-Verilog
Behavioral Modeling
Post-Synthesis Design Validation
Extract Parasitics
Simulation/Functional
Verification
Post-Synthesis Timing Verification
Post-Layout Timing Verification
Design Integration &
Verification
Test Generation & Fault Simulation
Design Sign-Off
Front End
Production-Ready Masks
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Huai-Yi Hsu

17. System Specification From CIC Digital IC Design Flow 2004.02.27
Huai-Yi Hsu

18. Algorithm Mapping System Level RTL Level From CIC
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19. Gate and Circuit Level Design
From CIC
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20. Physical Design
From CIC
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21. Register Transfer Level
Behavioral Model
System
concept
Algorithm
Increasing
detailed
realization &
complexity
Architecture
Increasing
behavioral
abstraction
Register Transfer Level
Gate Level
Transistor Level
Digital IC Design Flow
Huai-Yi Hsu

22. Design Domain Behavioral level of abstraction Design Model Domain
Physical
Structural
System
Algorithm
RTL
Gate
Switch
Architecture
Design
Logic
Layout
Verification
Synthesis
RTL level
Logic level
Digital IC Design Flow
Huai-Yi Hsu

23. Introduction to HDL HDL – Hardware Description Language
Why use an HDL ?
Hardware is becoming very difficult to design directly
HDL is easier and cheaper to explore different design options
Reduce time and cost
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Huai-Yi Hsu

24. Verilog HDL Brief history of Verilog HDL
1985: Verilog language and related simulator Verilog-XL were developed by Gateway Automation
1989: Cadence Design System purchased Gateway Automation
1990: Cadence released Verilog HDL to public domain
1990: Open Verilog International (OVI) formed
1995: IEEE standard 1364 adopted
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Huai-Yi Hsu

25. Verilog HDL
Feature
HDL has high-level programming language constructs and constructs to describe the connectivity of your circuit.
Ability to mix different levels of abstraction freely
One language for all aspects of design, test, and verification
Functionality as well as timing
Concurrency perform
Support timing simulation
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Huai-Yi Hsu

26. Compared to VHDL Verilog and VHDL are comparable languages
VHDL has a slightly wider scope
System-level modeling
Exposes even more discrete-event machinery
VHDL is better-behaved
Fewer sources of non-determinism (e.g., no shared variables ???)
VHDL is harder to simulate quickly
VHDL has fewer built-in facilities for hardware modeling
VHDL is a much more verbose language
Most examples don’t fit on slides
Digital IC Design Flow
Huai-Yi Hsu

27. The Verilog Language
Originally a modeling language for a very efficient event-driven digital logic simulator
Later pushed into use as a specification language for logic synthesis
Now, one of the two most commonly-used languages in digital hardware design (VHDL is the other)
Combines structural and behavioral modeling styles
Digital IC Design Flow
Huai-Yi Hsu

28. Different Levels of Abstraction
Architectural / Algorithmic
A model that implements a design algorithm in high-level language constructs
Register Transfer Logic (RTL)
A model that describes the flow of data between registers and how a design process these data.
Gate
A model that describe the logic gates and the interconnections between them.
Switch
A model that describes the transistors and the interconnections between them.
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29. Verilog HDL Behavior Language
Structural and procedural like the C programming language
Used to describe algorithm level and RTL level Verilog models
Key features
Procedural constructs for conditional, if-else, case, and looping operations.
Arithmetic, logical, bit-wise, and reduction operations for expressions.
Timing control.
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30. Verilog HDL Structural Language
Used to describe gate-level and switch-level circuits.
Key features
A complete set set of combinational primitives
Support primitive gate delay specification
Support primitive gate output strength specification
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31. Language Conventions Case-sensitivity
Verilog is case-sensitive.
Some simulators are case-insensitive
Advice: - Don’t use case-sensitive feature!
Keywords are lower case
Different names must be used for different items within the same scope
Identifier alphabet:
Upper and lower case alphabeticals: a~z A~Z
Decimal digits: 0~9
Underscore: _
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32. Language Conventions (cont’d)
Maximum of 1024 characters in identifier
First character not a digit
Statement terminated by ;
Free format within statement except for within quotes
Comments:
All characters after // in a line are treated as a comment
Multi-line comments begin with /* and end with */
Compiler directives begin with // synopsys XXX
Built-in system tasks or functions begin with $
Strings enclosed in double quotes and must be on a single line “Strings”
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33. Design Encapsulation
Encapsulate structural and functional details in a module
Encapsulation makes the model available for instantiation in other modules
module my_design (ports_list);
... // Declarations of ports go here
... // Structural and functional details go here
endmodule
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Huai-Yi Hsu

34. Port Declaration Three port types Input port Output port
input a;
Output port
output b;
Bi-direction port
inout c;
net
input
output
inout
reg or net
module
Port list
module full_add (S, CO, A, B, CI) ;
output S, CO ;
input A, B, CI ;
--- function description ---
endmodule
Port Declaration
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35. Two Main Data Types Nets represent connections between things
Do not hold their value
Take their value from a driver such as a gate or other module
Cannot be assigned in an initial or always block
Regs represent data storage
Behave exactly like memory in a computer
Hold their value until explicitly assigned in an initial or always block
Never connected to something
Can be used to model latches, flip-flops, etc., but do not correspond exactly
Shared variables with all their attendant problems
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Huai-Yi Hsu

36. Primitive Cells Primitives are simple modules
Verilog build-in primitive gate
not, buf:
Variable outputs, single input (last port)
and, or, buf, xor, nand, nor, xnor:
Single outputs (first port), variable inputs
module full_add (S, CO, A, B, CI) ;
--- port Declaration ---
wire net1, net2, net3;
xor U0(S,A,B,CI);
and U1(net1, A, B);
and U2(net2, B, CI);
and U3(net3, CI, A);
or U4(CO, net1, net2, net3);
endmodule
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Huai-Yi Hsu

37. How Are Simulators Used?
Testbench generates stimulus and checks response
Coupled to model of the system
Pair is run simultaneously
Testbench
System Model
Stimulus
Response
Result checker
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Huai-Yi Hsu

38. Example: Testbench module t_full_add(); wire sum, c_out;
reg a, b, cin; // Storage containers for stimulus waveforms
full_add M1 (sum, c_out, a, b, cin); //UUT
initial begin // Time Out
#200 $finish; // Stopwatch
end
initial begin // Stimulus patterns
#10 a = 0; b = 0; cin = 0; // Statements execute in sequence
#10 a = 0; b = 1; cin = 0;
#10 a = 1; b = 0; cin = 0;
#10 a = 1; b = 1; cin = 0;
#10 a = 0; b = 0; cin = 1;
#10 a = 0; b = 1; cin = 1;
#10 a = 1; b = 0; cin = 1;
#10 a = 1; b = 1; cin = 1;
endmodule
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39. Verilog Simulator
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40. Event-Driven Simulation
A change in the value of a signal (variable) during simulation is referred to as an event
Spice-like analog simulation is impractical for VLSI circuits
Event-driven simulators update logic values only when signals change
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41. Styles Structural - instantiation of primitives and modules
RTL/Dataflow - continuous assignments
Behavioral - procedural assignments
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42. Structural Modeling
When Verilog was first developed (1984) most logic simulators operated on netlists
Netlist: list of gates and how they’re connected
A natural representation of a digital logic circuit
Not the most convenient way to express test benches
Digital IC Design Flow
Huai-Yi Hsu

43. Behavioral Modeling A much easier way to write testbenches
Also good for more abstract models of circuits
Easier to write
Simulates faster
More flexible
Provides sequencing
Verilog succeeded in part because it allowed both the model and the testbench to be described together
Digital IC Design Flow
Huai-Yi Hsu

44. Style Example - Structural
module full_add (S, CO, A, B, CI) ;
output S, CO ;
input A, B, CI ;
wire N1, N2, N3;
half_add HA1 (N1, N2, A, B),
HA2 (S, N3, N1, CI);
or P1 (CO, N3, N2);
endmodule
module half_add (S, C, X, Y);
output S, C ;
input X, Y ;
xor (S, X, Y) ;
and (C, X, Y) ;
endmodule
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45. Style Example – Dataflow/RTL
module fa_rtl (S, CO, A, B, CI) ;
output S, CO ;
input A, B, CI ;
assign S = A ^ B ^ CI; //continuous assignment
assign CO = A & B | A & CI | B & CI; //continuous assignment
endmodule
Digital IC Design Flow
Huai-Yi Hsu

46. Style Example – Behavioral
module fa_bhv (S, CO, A, B, CI) ;
output S, CO ;
input A, B, CI ;
reg S, CO; // required to “hold” values between events.
or B or CI) //;
begin
S <= A ^ B ^ CI; // procedural assignment
CO <= A & B | A & CI | B & CI; // procedural assignment
end
endmodule
Digital IC Design Flow
Huai-Yi Hsu

47. How Verilog Is Used
Virtually every ASIC is designed using either Verilog or VHDL (a similar language)
Behavioral modeling with some structural elements
“Synthesis subset”
Can be translated using Synopsys’ Design Compiler or others into a netlist
Design written in Verilog
Simulated to death to check functionality
Synthesized (netlist generated)
Static timing analysis to check timing
Digital IC Design Flow
Huai-Yi Hsu

48. An Example: Counter Digital IC Design Flow 2004.02.27 Huai-Yi Hsu
`timescale 1ns/1ns
module counter;
reg clock; // declare reg data type for the clock
integer count; // declare integer data type for the count
initial // initialize things - this executes once at start
begin
clock = 0; count = 0; // initialize signals
#340 $finish; // finish after 340 time ticks
end
/* an always statement to generate the clock, only one statement follows the always so we don't need a begin and an end */
always
#10 clock = ~ clock; // delay is set to half the clock cycle
/* an always statement to do the counting, runs at the same time (concurrently) as the other always statement */
// wait here until the clock goes from 1 to 0
@ (negedge clock);
// now handle the counting
if (count == 7)
count = 0;
else
count = count + 1;
$display("time = ",$time," count = ", count);
endmodule
Digital IC Design Flow
Huai-Yi Hsu

49. An Example: Counter (cont’d)
Verilog using ModelSim
Assume working directory: VlogExamples/Counter
Invoke ModelSim
Change Directory to VlogExamples/Counter
Copy file counter.v to the working directory
Create a design library: vlib work
Compile counter.v: vlog counter.v
Start the simulator: vsim counter
Run the simulation: e.g., run 200ns
> run 200
# time = count =
# time = count =
# time = count =
# time = count =
# time = count =
# time = count =
# time = count =
# time = count =
# time = count =
# time = count =
Digital IC Design Flow
Huai-Yi Hsu

50. ModelSim Simulator Creating a Project
Select Create a Project from the Welcome to ModelSim dialog box.
Or select File >New > Project from the ModelSim Main window.
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51. Add File to Project
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52. Compile
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53. Load Design
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54. List Signals
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55. Run Simulation
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56. Silos Verilog Logic Simulator
Free HDL simulator
Web:
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57. Edit Verilog Files
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58. Create New Project
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59. Add File to Project
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60. Starting Simulation
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61. Silos Overview
Silos is a logic simulation environment developed for use in the design and verification of electronic circuits and systems.
Silos can simulate designs at the behavioral, gate and switch levels that are modeled with the Verilog Hardware Description Language (HDL).
Silos can back annotate delays specified using the Standard Delay Format (SDF).
Digital IC Design Flow
Huai-Yi Hsu

62. Debugging Capabilities
The mouse cursor can be held over variables and expressions in the source code to directly see their value at a time point.
Drag and drop variables and expressions directly from the source file into the Data Analyzer waveform window, or from the Silos Explorer to the Data Analyzer window to provides easy access to the simulation results.
Unlimited traceback for behavioral and gate designs quickly isolates the cause of Unknown levels.
A graphical Finite State Machine entry, source code generation, documentation, and debugging tool.
Code Coverage reporting for Line reports and Operator reports display a purple dot beside any line or operator that was not executed by the testbench.
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63. Summary IC design flow History of Verilog-HDL Verilog simulator
Next course
Basic concept of Verilog-HDL
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Huai-Yi Hsu

64. Homework #0 Download the Verilog Simulator
Setup the Verilog simulation environment.
Opening new project
Add Verilog file to project
Run simulation
Website:
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Huai-Yi Hsu

65. Multiplexer Built From Primitives
Verilog programs built from modules
module mux(f, a, b, sel);
output f;
input a, b, sel;
and g1(f1, a, nsel),
g2(f2, b, sel);
or g3(f, f1, f2);
not g4(nsel, sel);
endmodule
Each module has an interface
Module may contain structure: instances of primitives and other modules a f1
nsel g1 g4 f g3 b g2
sel f2
Digital IC Design Flow
Huai-Yi Hsu

66. Multiplexer Built From Primitives
module mux(f, a, b, sel);
output f;
input a, b, sel;
and g1(f1, a, nsel),
g2(f2, b, sel);
or g3(f, f1, f2);
not g4(nsel, sel);
endmodule
Identifiers not explicitly defined default to wires a f1
nsel g1 g4 f g3 b g2
sel f2
Digital IC Design Flow
Huai-Yi Hsu

67. Multiplexer Built With Always
Modules may contain one or more always blocks
module mux(f, a, b, sel);
output f;
input a, b, sel;
reg f;
or b or sel)
if (sel) f = b;
else f = a;
endmodule
Sensitivity list contains signals whose change triggers the execution of the block a f b
sel
Digital IC Design Flow
Huai-Yi Hsu

68. Multiplexer Built With Always
module mux(f, a, b, sel);
output f;
input a, b, sel;
reg f;
or b or sel)
if (sel) f = a;
else f = b;
endmodule
A reg behaves like memory: holds its value until imperatively assigned otherwise
Body of an always block contains traditional imperative code a f b
sel
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Huai-Yi Hsu

69. Mux with Continuous Assignment
module mux(f, a, b, sel);
output f;
input a, b, sel;
assign f = sel ? a : b;
endmodule
LHS is always set to the value on the RHS
Any change on the right causes reevaluation a f b
sel
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Huai-Yi Hsu

70. Mux with User-Defined Primitive
primitive mux(f, a, b, sel);
output f;
input a, b, sel;
table
1?0 : 1;
0?0 : 0;
?11 : 1;
?01 : 0;
11? : 1;
00? : 0;
endtable
endprimitive
Behavior defined using a truth table that includes “don’t cares”
This is a less pessimistic than others: when a & b match, sel is ignored
(others produce X) a f b
sel
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Huai-Yi Hsu

71. GLITCHES AND STATIC HAZARDS
The output of a combinational circuit may make a transition even though the patterns applied at its inputs do not imply a change. These unwanted switiching transients are called "glitches."
Glitches are a consequence of the circuit structure and the application of patterns that cause the glitch to occur. A circuit in which a glitch may occur under the application of appropriate inputs signals is said to have a hazard.
A static 1-hazard occurs if an output has an initial value of 1, and an input pattern that does not imply an output transition causes the output to change to 0 and then return to 1.
A static 0-hazard occurs if an output has an initial value of 0, and an input pattern that does not imply an output transition causes the output to change to 1 and then return to 0.
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72. For the hazard-free cover: F = AC + BC' + AB
STATIC HAZARDS
Static hazards are caused by differential propagation delays on reconvergent fanout paths.
Static hazards can be eliminated by introducing redundant cubes in the cover of the output expression (the added cubes are called a hazard cover).
A "minimal"realization:
F = AC + BC'
For the hazard-free cover: F = AC + BC' + AB
Digital IC Design Flow
Huai-Yi Hsu

73. DYNAMIC HAZARDS (Multiple glitches)
A circuit has a dynamic hazard if an input transition is supposed to cause a single transition in an output, but causes two or more transitions before reached its expected value.
Dynamic hazards are a consequence of multiple static hazards caused by multiply reconvergent paths in a multilevel circuit.
Dynamic hazards are not easy to eliminate.
Elimination of all static hazards eliminates dynamic hazards.
Approach: Transform a multilevel circuit into a two-level circuit and eliminate all of the static hazards.
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74. Example
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75. STORAGE ELEMENTS: R-S LATCH
Storage elements are used to store information in a binary format (e.g. state, data, address, opcode, machine status).
Storage elements may be clocked or unclocked.
Two types: level-sensitive, edge-sensitive
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76. STORAGE ELEMENTS: TRANSPARENT LATCHES
Latches are level-sensitive storage elements; data storage is dependent on the level (value ) of the input clock (or enable) signal. The output of a transparent latch changes in response to the data input while the latch is enabled. Changes at the input are visible at the output data
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77. STORAGE ELEMENTS: FLIP-FLOPS
Flip-flops are edge-sensitive storage elements; data storage is synchronized to an edge of a clock. The value of data stored depends on the data that is present at the data input(s) when the clock makes a transition at its active (rising or falling) edge.
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78. MASTER-SLAVE FLIP-FLOP
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