1. 1 Gbit/s Serial Link 1 Gbit/s Data Link Using Multi Level Signalling
Mila LAMOURET
(CNRS IN2P3 MICHRAU)‏ 1

2. HSL – Bloc diagram and Specifications
The specific application of the circuit is to perform the high speed data transmission over small distances
1 Gb/s data transmission rate
low power consumption
Bloc diagram
Data Link Using Current Multi Level Signalling :
The required bandwidth of the channel for a given bit rate decreases
The maximum required on-chip clock frequency is reduced

3. DAC – Bloc diagram and Specifications
Differential Current Steering DAC
0.13µm 8RF-DM IBM Process
Internal Temperature Independent Reference
Output type - Current
Resolution 4 bits
Clock frequency 250 MHz
Analog Voltage 1,6 V
Logic Voltage 1,6 V
Switched Current Sources
Current Source
4 bit Thermometer Decoder
Temperature Independent Current Reference
CLK
250 MHz
AWK
Additional bit B0 B1 B2 B3 16 In Ip

4. DAC – Unit Cell Binary to Thermometric Encoding is Applied in order:
to decrease the glitches
to have better matching between the current slave cells – improving the monotonicity and the DNL
Analog Part of the Unit Cell
NMOS Cascoded Current Mirror Slave biased by Internal Temperature Independent Reference
Differential NMOS Switch
Digital Part of the Unit Cell
The Digital part of the unit cell is applied to avoid the glitches due to the propagation time delay between the thermometric bits TN

5. Temperature Independent Current Reference
Current Variation
+/- 0.44%
Current Steering DAC
Current Master
In order to decrease the variation of the DAC output current in temperature Temperature Independent Current Reference is used
The transistors (T15-T25) generate a current which is proportional to the mobility
The transistors (T5-T14) generate a current which is inversely proportional to the mobility

6. DAC – Simulation Results
4 Bits DAC Input
Current DAC Output
Current DAC Output Variation in Temperature
ΔMAX=+0.27%

7. ADC – Bloc diagram and specifications
Differential Current Input ADC
Architecture - Flash
0.13µm 8RF-DM IBM Process
Resolution 4 bits
Clock frequency 250 MHz
Analog Voltage 1,6 V
Logic Voltage 1,6 V
Voltage Reference
ADC Control Block
Comparators Block
Thermometer 4 bit Decoder B0 B1 B2 B3 16
ADC Input Block – Differential Current Pair
Cen
Cawk
CLK
250 MHz

8. Latched Comparators Input Voltage
ADC – Input Stage
ADC Input Current
Latched Comparators Input Voltage

9. Latched Comparator Sensitivity
~ 20mV
In the presented simulations
the Clock is boosted to 500 MHz

10. Reducing Consumption - Stand-by mode
Voltage Reference
ADC Control Block
Thermometer 4 bit Decoder B0 B1 B2 B3 16
ADC Input Block – Differential Current Pair
Cen
Cawk
CLK
250 MHz
Comparators Block In Ip
One cycle before sending the data, additional bit must be sent to the DAC to “Awake” the ADC

11. Top Simulation Results
Post-layout Simulation Results taking in to
account the pad-ring and packaging effects
RMS_CONSO_ANALOG_ENBLD=2.7mA
RMS_CONSO_LOGIC_ENBLD=8.4mA
RMS_CONSO_ANALOG_AWKD=4.6mA
RMS_CONSO_ANALOG_AWKD=16.3mA
ADC Input Current
DAC Input Data
ADC Output Data
Consumption

12. First Prototype Layout Sent to be Processed
Conclusion
First Prototype Layout Sent to be Processed
0.13µm 8RF-DM IBM Process
Size ~1 mm2
ADC
DAC