1. Figure 5. 1 An example of AND-OR logic
Figure An example of AND-OR logic. Open file F05-01 to verify the operation.

2. Figure 5.2

3. Figure 5. 3 An AND-OR-Invert circuit produces a POS output
Figure An AND-OR-Invert circuit produces a POS output. Open file F05-03 to verify the operation.

4. Figure 5.4

5. Figure 5. 5 Exclusive-OR logic diagram and symbols
Figure Exclusive-OR logic diagram and symbols. Open file F05-05 to verify the operation.

6. Figure 5. 6 Two equivalent ways of implementing the exclusive-NOR
Figure Two equivalent ways of implementing the exclusive-NOR. Open files F05-06 (a) and (b) to verify the operation.

7. Figure 5.7 Even-parity generator.

8. Figure 5.8 Even-parity checker.

9. Figure 5.9 Logic circuit for X = AB + CDE.

10. Figure 5.10 Logic circuits for X = AB(CD + EF) = ABCD + ABEF._ _
Figure Logic circuits for X = AB(CD + EF) = ABCD + ABEF.

11. _ _ _
Figure Logic circuit for Open file F05-11 to verify the operation. X = ABC + ABC.

12. Figure 5.12 Open file F05-12 to verify the operation.

13. Figure 5.13 Open file F05-13 to verify the operation.

14. Figure Open file F05-14 to verify that this circuit is equivalent to the circuit in Figure 5–15.

15. Figure 5.15

16. Figure 5.16

17. Figure 5.17

18. Figure 5. 18 Universal application of NAND gates
Figure Universal application of NAND gates. Open files F05-18(a), (b), (c), and (d) to verify each of the equivalencies.

19. Figure 5. 19 Universal application of NOR gates
Figure Universal application of NOR gates. Open files F05-19(a), (b), (c), and (d) to verify each of the equivalencies.

20. Figure 5.20 NAND logic for X = AB + CD.

21. Figure 5.21 Development of the AND-OR equivalent of the circuit in Figure 5–20.

22. Figure 5.22 Illustration of the use of the appropriate dual symbols in a NAND logic diagram.

23. Figure 5.23

24. Figure 5.24

25. Figure 5.25

26. Figure 5.26 NOR logic for X = (A + B)(C + D).

27. Figure 5.27

28. Figure 5.28 Illustration of the use of the appropriate dual symbols in a NOR logic diagram.

29. Figure 5.29

30. Figure 5.30

31. Figure 5.31

32. Figure 5.32

33. Figure 5.33

34. Figure 5.34

35. Figure 5.35

36. Figure 5.36

37. Figure 5.37 Illustration of a node in a logic circuit.

38. Figure 5. 38 Open output in driving gate
Figure Open output in driving gate. Assume a HIGH is on one gate input.

39. Figure 5.39 Open input in a load gate.

40. Figure 5.40 Shorted output in the driving gate or shorted input in a load gate.

41. Figure Example of signal tracing and waveform analysis in a portion of a printed circuit board. TP indicates test point.

42. Figure 5.42

43. Figure Simplified comparison of the VHDL structural approach to a hardware implementation. The VHDL signals correspond to the interconnections on the circuit board, and the VHDL components correspond to the IC devices.

44. Figure Predefined programs for a 2-input AND gate and a 2-input OR gate to be used as components in the data flow approach.

45. Figure 5.45

46. Figure Illustration of the instantiation statements and port mapping applied to the AND-OR logic. Signals are shown in red.

47. Figure 5.47

48. Figure A VHDL program for a combinational logic circuit after entry on a generic text editor screen that is part of a software development tool.

49. Figure A typical waveform editor tool showing the simulated waveforms for the logic circuit described by the VHDL code in Figure 5–48.

50. Figure 5.50 Tank with level and temperature sensors and controls.

51. Figure 5.51 Multisim circuit screen for the valve control logic.

52. Figure 5.52 Block diagram for temperature control circuit.

53. Figure 5.53 Logic diagram of the temperature control logic.

54. Figure 5.54

55. Figure 5.55

56. Figure 5.56

57. Figure 5.57

58. Figure 5.58

59. Figure 5.59

60. Figure 5.60

61. Figure 5.61

62. Figure 5.62

63. Figure 5.63

64. Figure 5.64

65. Figure 5.65

66. Figure 5.66

67. Figure 5.67

68. Figure 5.68

69. Figure 5.69

70. Figure 5.70

71. Figure 5.71

72. Figure 5.72

73. Figure 5.73

74. Figure 5.74

75. Figure 5.75

76. Figure 5.76

77. Figure 5.77

78. Figure 5.78

79. Figure 5.79