1. Introduction to the Balanced Gamma (BG) Switch for Broadband Communications
A Presentation for the Advanced Data Networks (ENGI 9867)
Presented by
Cheng Li
The Computer Engineering Research Laboratories (CERL)
Faculty of Engineering and Applied Science
Memorial University of Newfoundland
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

2. Multicast in Broadband Packet Switching Network
Gateway Networks
Network B
Network C
Data Networks
Network D
Network A
Gateway Networks
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

3. High-Speed Packet Switch Classification
Packet Switches
Time Division
Space Division
Shared
Memory
Medium
MIN SN
Single-Path
MIN Design
Multi-Path L
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

4. Multicast Switches Classification
Cascaded Approach
Integrated Approach
Starlite Switch
Knockout Switch
Turner’s Broadcast Packet Switch
Lee’s Multicast Switch
SCCQ Multicast Switch
LGMIN Switch
Multinet Switch
Recursive Multistage Structured Multicast Switch
Three-Stage Clos Multicast Switch
MOBAS Switch
Abacus Switch
PINIUM Switch
SCCQ: Shared Concentration and Output Queueing
LGMIN: Link-Grouped MIN Switch
MOBAS: Multicast Output Buffered ATM Switch
PINIUM: Prioritized Services, Internal Non- blocking, Internally Un-buffered Multicast Switch
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

5. General Model for the Packet Switches
CAC: Connection Admission
Control
SM: System Management
CAC SM
IPC: Input Port Controller
OPC: Output Port Controller
IPC
OPC
IPC
OPC
Switch
Fabric . .
Switch Fabric – Core of Switching Nodes
Hardware implementation is required
Efficient switch fabrics are characterized by their high throughput, low delay, small delay jitter, low cell loss, and scalability
Switch Fabric is the Core of Switching Nodes and the center part of the whole switching network
For broadband packet switching networks, the link speed usually goes to several hundred mega bytes or even giga bytes, hardware implementation is a general requirement for the switch fabric design
IPC
OPC
SF: Switch Fabric
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

6. Switch Fabrics – Core of Switching Nodes
Center part of the whole switching network.
Hardware implementation is required.
Less efficient switch fabrics lead to poor performance.
Efficient switch fabrics are characterized by their high throughput, low delay, low delay jitter, low cell loss, and scalability.
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

7. Target: An Innovative High-Performance Multicast Switch
Architecture Design
Architecture Justification
Routing, Replication and Acknowledgement
Scalable Architecture
Target: An Innovative High-Performance Multicast Switch
Performance Evaluation
Multicast Traffic Model
Analytical Modeling
Performance Analysis
VLSI Design
Chip Design
Simulation and Testing
Implementation
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

8. 8  8 Multicast BG Switch Architecture1 2 3 4 5 6 7
Stage 0
Stage 1
Stage 2
Output Stage
Output 0
Output 1
Output 2
Output 3
Output 4
Output 5
Output 6
Output 7
Input 0
Input 1
Input 2
Input 3
Input 4
Input 5
Input 6
Input 7
IPC
OPC
Input Port Controllers (IPCs)
Switch Fabric (SF)
Output Port Controllers (OPCs)
(1) Key Design Aspects Of Multicast Switch Fabric
-- High efficient cell routing and replication mechanism
-- Accurate and efficient acknowledgement mechanism
-- Ease of hardware implementation and scalability
(2) The BG Multicast Switch
-- No dedicated copy network
-- Implicit cell routing and replication inside the SF
-- Unlike Banyan network, BG utilizes basically 4x4 SE
-- Basic architecture for N x N Switch consists of
N IPCs, an N x N MIN based SF, and N OPCs
(3) SF consists of n+1 stages, n=log2(N), each stage N SEs
-- 1 x 2 SEs for Stage 0, 2 x 4 SEs for Stage 1, and 4 x 4 SEs for the following n-2 stages. The last stage is the output buffer stage which can accept up to 4 cells per output port in one switching cycle.
(4) Internal bandwidth expansion through the first 2 stage
-- Reason for good performance and reasonable HW complexity
-- Move on to architecture choice justification
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

9. OPC Request Probability Distribution under Multicast Bursty Traffic
Through simulation results. Mean Burst Length is 5, Mean Fanout is 2, Traffic Load is 100%
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

10. SE Self-Routing and Self-Replication
Output Link 0
Output Link 1
There are three types of SEs in the SF. 1x2 and 2x4 SEs can be treated as a special (simpler) case of the 4x4 SEs. So, the SEs are mainly studied.
The four outputs of the 4x4 SEs are divided into 2 link groups: the upper link group (link 0 and 1) and the lower link group (link 2 and 3). Link 0 and Link 2 are the regular links of the link group while Link 1 and 3 are the alternative links. Regular link will be always assigned first whenever there is a cell request for the link group.
Priority routing is feature considered in the switch fabric design. Currently, up to 8 levels of priorities are supported and it is very easy to be further expanded.
When switching, the SE sort input requests based on the priorities. Cell with the highest priority will be always assigned with output link resources first. In this example, cell C, which has a priority level 3, is processed first. By checking the routing and replication tag, which is 01, means request upper link with no replication. So link 0, which is the regular link for upper link group, is assigned to cell C. similar, we process cell b and a. for cell a, the tag is 11, which means replication should be done, and it will be forwarded to the alternative links of both link groups.
When all the link resources are used up, further requests will be blocked and blocking will occur. Blocked cell will be kept in the HOL at the input queue and will be switched for the next switching cycle.
Output Link 2
Output Link 3
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

11. Dynamic-length Self-Routing & Replication Algorithm for an 8  8 Multicast BG Switch1 2 3 4 5 6 7
Stage 0
Stage 1
Stage 2
Output Stage 01 10
Port 7
Port 0
0010 10
1.0
1.1
1.2
( ) 11 √ 11 01
1101 01 √ 11 11 √ √
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

12. A R C H I T E U L S C A L B I T Y November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

13. Target: An Innovative High-Performance Multicast Switch
Architecture Design
Architecture Justification
Routing, Replication and Acknowledgement
Scalable Architecture
Target: An Innovative High-Performance Multicast Switch
Performance Evaluation
Multicast Traffic Model
Analytical Modeling
Performance Analysis
VLSI Design
Chip Design
Simulation and Testing
Implementation
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

14. Performance Evaluation
Under uniform and non-uniform multicast traffic, with random and bursty cell arrival.
Traffic load defined at switch output port
Offered load to switch output is associated with load at the input via mean fanout of multicast traffic, i.e.,
Compared with ideal non-blocking output buffered multicast switch and other published switches
Ideal non-blocking network satisfies all the input requests if there is space in the output buffer
Abacus switch and PINIUM switch (Published on JSAC’97)
Performance metrics
Average and Maximum Cell Delay
Cell Loss Ratio
Average and Maximum Input / Output Buffer Requirements
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

15. Network Traffic Models
Proper traffic models are critical for performance comparison between different architectures
Key aspects in a traffic model
Traffic load behavior
Bursty nature and correlation in traffic arrivals
Traffic destination selection distribution
Distribution of traffic QoS classes
Proportion of unicast and multicast traffic and their characteristics
Network Processing Forum (NPF)
Founded in February 2001 by merging to former industrial groups
Common Programming Interface Forum (CPIX)
Common Switch Interface Consortium (CSIX)
Develop benchmark framework for switch design, testing, and comparison
Switch fabric benchmarking framework approved in July 2003
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

16. Traffic Type Model * ** ** November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

17. Multicast Bursty Traffic
Described by three independent processes
Arrival process
ON - OFF Bursty Traffic Model
Fanout distribution process
Truncated Geometric Distribution
Destination selection process
Random
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

18. Bursty Traffic ON-OFF Model
On Period
Off Period
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

19. Analytical Modeling Under multicast random traffic condition
Random (non-bursty) cell arrival
Truncated geometric distributed multicast cell fanout
Uniformly distributed cell destination
Analysis following the three-phase backpressure switching operation
Cell blocking probabilities at SEs of different stages as well as for the whole switch fabric are analyzed
Output queue analysis using discrete-time Markov chain
Input queuing analysis using discrete-time Markov chain
Obtain overall performance measures
1. Analytical modeling provides a good method to validate simulation results theoretically.
2. Even though an exact analytical model is very hard to obtain for a complicated system like the BG switch, it is possible to perform an analysis under some loosened conditions and preserve enough accuracy.
3. Cell blocking probability for the whole SF and the traffic arrival probability on the four links feeding each output queue is obtained
4. Cell blocking probability, queue occupancy and queue delay at the output queue will be obtained through output queue analysis
5. Then the overall cell blocking probability for the combined SF and output queue is calculated, which is the probability of cells being kept in the HOL position of the input queue
6. Input queueing analysis to obtain cell loss probability and other performance measures.
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

20. Finite Input Queue Analysis
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

21. Loss Performance Comparison
Traffic condition:
Switch Size: 128 x Traffic Load: 90 % Mean Fanout: 2 Output Buffer: 500 Duration: One Billion cells
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

22. Loss Performance Under MBT
Traffic condition:
Switch Size: 128 x Traffic Load: 90% Burstiness: 5 Output Buffer: Duration: One Billion cells
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

23. Delay Performance Under MBT
Traffic condition:
Traffic Load: 90% Fanout: 2 Burstiness: 5 IB Size: 300 OB Size: Duration: One Billion cells
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

24. Target: An Innovative High-Performance Multicast Switch
Architecture Design
Architecture Justification
Routing, Replication and Acknowledgement
Scalable Architecture
Target: An Innovative High-Performance Multicast Switch
Performance Evaluation
Multicast Traffic Model
Analytical Modeling
Performance Analysis
VLSI Design
Chip Design
Simulation and Testing
Implementation
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

25. Digital IC Design Flow From CMC
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

26. Design and Implementation
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

27. Switch Element (4 x 4) Architecture
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

28. Switch Element Functional Simulation
Example shown for SEs at Stage 0 of 16 x 16 BG switch
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

29. Multicast BG Switch Functional Testing
Not possible to verify results through waveform observation, alternative approach must be used
Testing Methodology
Data files are used by testbench file for multicast BG switch to emulate input/output buffers
During HW simulation, Tag, ACK, and Payload information at switch input and output are recorded in files during each switching cycle for future analysis
High level language (C/C++) is used to generate data randomly as well as analyze HW simulation results
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

30. VLSI Design Implemented using 0.18 µm CMOS technology
Hardware complexity and Timing
Switch (16 x 16) synthesized using 5 ns clock, which yield an aggregated switching capacity for single plane 16 x 16 BG Multicast switch at around 3.2 Gbps
Stage components are synthesized under the same clock for hardware complexity estimation for larger switch sizes
Core logic area in square microns is converted to gate count via two-input nAND gate
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

31. Hardware Complexity
Synthesized result for 16 x 16 multicast BG switch (in gates)
*: Estimated result for Larger switches
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications

32. Conclusions New implicit multicast switch architecture
New self-routing and replication algorithm and acknowledgement algorithm
Outstanding performance of the multicast BG switch
Analytical modeling for performance analysis
Realizable and scalable switch architecture
November 16, 2018
Design, Modeling and Analysis of the Multicast BG Switch for Broadband Communications