1. Desired Bode plot shape
High low freq gain for steady state tracking
Low high freq gain for noise attenuation
Sufficient PM near wgc for stability
Type
ess requirement
wgc
td, tr, tp, ts w
0dB w
-90
PM=70-Mp
-180

2. Overall Loop shaping strategy
Overall gain K to select wgc
By shifting gain plot up and down
PD or lead to add more wgc
Both PD and lead has positive phase
PI or lag to increase low freq gain
But both has negative phase,
deteriorates PM
Low pass filter to reduce high freq gain
For noise attenuation
Also has negative effect on PM

3. Lead Controller Design

4. Goal: select z and p so that max phase lead is at desired wgc
plead
zlead
20log(Kzlead/plead)
Goal: select z and p so that max phase lead is at desired wgc
and max phase lead = PM defficiency!

6. Lead Design From specs => PMd and wgcd From plant, draw Bode plot
Find PMhave = angle(G(jwgcd)
DPM = PMd - PMhave + a few degrees
Choose a=plead/zlead so that fmax = DPM and it happens at wgcd

7. Lead design example Plant transfer function is given by:
n=[50000]; d=[ ];
Desired design specifications are:
Step response overshoot <= 16%
Closed-loop system BW>=20;

8. n=[50000]; d=[ ]; G=tf(n,d);
figure(1); margin(G);
Mp_d = 16;
PMd = 70 – Mp_d ;
BW_d=20;
w_gcd = BW_d*0.7; Gwgc=evalfr(G, j*w_gcd);
PM = pi+angle(Gwgc);
phimax= PMd*pi/180-PM;
alpha=(1+sin(phimax))/(1-sin(phimax));
zlead= w_gcd/sqrt(alpha);
plead=w_gcd*sqrt(alpha);
K=sqrt(alpha)/abs(Gwgc);
ngc = conv(n, K*[1 zlead]);
dgc = conv(d, [1 plead]);
figure(1); hold on; margin(ngc,dgc); hold off;
[ncl,dcl]=feedback(ngc,dgc,1,1);
figure(2); step(ncl,dcl);

9. After design
Before design

10. Closed-loop Bode plot by:
margin(ncl*1.414,dcl);
Magnitude plot shifted up 3dB
So, gc is BW

12. Alternative use of lead
Use Lead and Proportional together
To fix overshoot and ess
No speed requirement
Select K so that KG(s) meet ess req.
Find wgc and PM, also find PMd
Determine phi_max, and alpha
Place phi_max a little higher than wgc

13. Alternative lead design example
Plant transfer function is given by:
n=[50]; d=[1/50 1 0];
Desired design specifications are:
Step response overshoot <= 20%
Steady state tracking error for ramp input <= 1/200;
No speed requirements
No settling concern
No bandwidth requirement

14. n=[50]; d=[1/5 1 0];
figure(1); clf; margin(n,d); grid; hold on;
Mp = 20;
PMd = 70 – Mp + 7;
ess2ramp= 1/200; Kvd=1/ess2ramp;
Kva = n(end)/d(end-1); Kzp = Kvd/Kva;
figure(2); margin(Kzp*n,d); grid;
[GM,PM,wpc,wgc]=margin(Kzp*n,d);
w_gcd=wgc; phimax = (PMd-PM)*pi/180;
alpha=(1+sin(phimax))/(1-sin(phimax));
z=w_gcd/alpha^.25; %sqrt(alpha); %phimax located higher
p=w_gcd*alpha^.75; %sqrt(alpha); %than wgc
ngc = conv(n, alpha*Kzp*[1 z]); dgc = conv(d, [1 p]);
figure(3); margin(tf(ngc,dgc)); grid;
[ncl,dcl]=feedback(ngc,dgc,1,1);
figure(4); step(ncl,dcl); grid;
figure(5); margin(ncl*1.414,dcl); grid;

21. Lead design tuning example
C(s)
G(s)
Design specifications: rise time <=2 sec
overshoot <16%

34. Desired tr < 2 sec
We had tr = 1.14 in the previous 4 designs
4. Go back and take wgcd = 0.6*wn
so that tr is not too small

35. n=[1]; d=[ ]; G=tf(n,d);
Mp_d = 16; %in percentage
PMd = 70 - Mp_d + 4; %use Mp + PM =70
tr_d = 2; wnd = 1.8/tr_d; w_gcd = 0.6*wnd;
Gwgc=evalfr(G, j*w_gcd);
PM = pi+angle(Gwgc);
phimax= PMd*pi/180-PM;
alpha=(1+sin(phimax))/(1-sin(phimax));
zlead= w_gcd/sqrt(alpha);
plead=w_gcd*sqrt(alpha);
K=sqrt(alpha)/abs(Gwgc);
ngc = conv(n, K*[1 zlead]);
dgc = conv(d, [1 plead]);
[ncl,dcl]=feedback(ngc,dgc,1,1);
stepchar(ncl,dcl); grid
figure(2); margin(G); hold on; margin(ngc,dgc); hold off; grid

38. Lag Controller Design

39. Desired effect: low freq gain boost for improved steady state tracking
z/p=40
Desired effect: low freq gain boost for improved steady state tracking
z/p=20
z/p=10
z=wgcd/5
wgcd
z/p=5
Kill PM by 10 to 12 deg

40. Desired effect: low freq gain boost for improved steady state tracking
z/p=40
Desired effect: low freq gain boost for improved steady state tracking
z/p=20
z/p=10
z=wgcd/10
wgcd
z/p=5
Kill PM by 5 to 7 deg

41. z/p=40
z/p=20
Want these:
DC gain boosting
z/p=10
z/p=5
z=wgcd/20
wgcd
Don’t want these:
PM reduction!
Kill PM by 2 to 3 deg

42. Lag and lead-lag Design Steps
From plant, draw Bode plot
From specs => PMd and wgcd
If there is speed or BW req,  wgcd,
In this case, if PM not enough, design PD or lead
Otherwise, choose wgcd to have PM>PMd
Find K to enforce wgcd:
Find Kp,v,a-have with K and C above
Find Kp,v,a-des from ess specs
zlag/plag = Kp,v,a-des/Kp,v,a-have
Let zlag= wgcd/10~20, depending on PM room
Compute plag

43. Lag design example Plant transfer function is given by:
Desired design specifications are:
Step response overshoot <= 10%
Steady state tracking error to ramp input is <=0.01
Note: no speed or BW requirement, so just choose wgcd to have enough PM

44. n=[1]; d=[1/5/50 1/5+1/50 1 0];
figure(1); clf; margin(n,d);
%proportional control design:
figure(1); hold on; grid; V=axis;
Mp = 10;
PMd = 70 – Mp + 3;
semilogx(V(1:2), [PMd-180 PMd-180],':r');
%get desired w_gc
x=ginput(1); w_gcd = x(1);
K = 1/abs(evalfr(tf(n,d),j*w_gcd));
Kva = K*n(end)/d(end-1); ess=0.01; Kvd=1/ess;
z = w_gcd/5; p = z/(Kvd/Kva);
ngc = conv(n, Kp*[1 z]); dgc = conv(d, [1 p]);
figure(1); hold on; margin(ngc,dgc);
[ncl,dcl]=feedback(ngc,dgc,1,1);
figure(2); step(ncl,dcl); grid;
figure(3); margin(ncl*1.414,dcl); grid;

46. Designed for 63
Lag killed 12

47. Overshoot too much

48. n=[1]; d=[1/5/50 1/5+1/50 1 0];
figure(1); clf; margin(n,d); hold on; grid; V=axis;
Mp = 10;
PMd = 70 – Mp + 3;
semilogx(V(1:2), [PMd-180 PMd-180],':r');
x=ginput(1); w_gcd = x(1); %get desired w_gc
K = 1/abs(polyval(n,j*w_gcd)/polyval(d,j*w_gcd));
Kva = K*n(end)/d(end-1); ess=0.01; Kvd=1/ess;
z = w_gcd/10; p = z/(Kvd/Kva);
ngc = conv(n, K*[1 z]); dgc = conv(d, [1 p]);
figure(1); hold on; margin(ngc,dgc);
[ncl,dcl]=feedback(ngc,dgc,1,1);
figure(2);step(ncl,dcl); grid;
figure(3); margin(ncl*1.414,dcl); grid;

51. clear all; n=[1]; d=[1/5/50 1/5+1/50 1 0];
figure(1); clf; margin(n,d); grid; V=axis; hold on;
Mp = 10;
PMd = 70 – Mp + 7;
semilogx(V(1:2), [PMd-180 PMd-180],':r');
x=ginput(1); w_gcd = x(1); %get desired w_gc
K = 1/abs(polyval(n,j*w_gcd)/polyval(d,j*w_gcd));
Kva = K*n(end)/d(end-1); ess=0.01; Kvd=1/ess;
z = w_gcd/10; p = z/(Kvd/Kva);
ngc = conv(n, K*[1 z]); dgc = conv(d, [1 p]);
figure(1); hold on; margin(ngc,dgc);
[ncl,dcl]=feedback(ngc,dgc,1,1);
figure(2);step(ncl,dcl); grid;
figure(3); margin(ncl*1.414,dcl); grid;

55. Lead-Lag design example
Plant transfer function is given by:
Desired design specifications are:
Step response overshoot <= 16%
Step response rise time <= 2 sec
Steady state tracking error to unit acceleration input is <=1
Note: we have all three types of specs:
speed, relative stability, and tracking

56. Strategy First do a lead design to fix speed and overshoot requirement
Then do a lag design to fix the ess.

57. n=[1]; d=[ ];
figure(1); clf; margin(n,d); grid; hold on;
Mp=16; PMd = 70 – Mp + 1;
tr = 2; wn = 1.8/tr; w_gcd = wn*0.8;
PM = pi+angle(evalfr(tf(n,d),j*w_gcd));
phimax = PMd*pi/180-PM;
alpha=(1+sin(phimax))/(1-sin(phimax));
zlead=w_gcd/sqrt(alpha); plead=w_gcd*sqrt(alpha);
K=sqrt(alpha)/(abs(evalfr(tf(n,d),j*w_gcd)));
ngc = conv(n, K*[1 zlead]); dgc = conv(d, [1 plead]);
figure(1); margin(ngc,dgc);
[ncl,dcl]=feedback(ngc,dgc,1,1);
figure(2); step(ncl,dcl); grid;
figure(3); margin(ncl*1.414,dcl); grid;

59. Need to reduce by Mp by 10%
So increase PMd by 10 deg

60. Overshoot is too large.
Plus, we know the lag controller will further deteriorate Mp.
So, redesign for better Mp.

63. About 12% overshoot.
So, let’s go ahead with lag design.

64. Kaa = ngc(end)/dgc(end-2); ess=1; Kad=1/ess;
zlag = w_gcd/20; plag = zlag/(Kad/Kaa);
ngcc = conv(ngc, [1 zlag]); dgcc = conv(dgc, [1 plag]);
figure(1); margin(ngcc,dgcc);
[ncl,dcl]=feedback(ngcc,dgcc,1,1);
figure(4); step(ncl,dcl); grid;
figure(5); margin(ncl*1.414,dcl); grid;
We don’t have too much room to spare for Mp, so choose 20 so that the lag controller only kills about 3 degrees of PM, which will add about 3 percentage points to Mp.

68. Lead-Lag design HW Desired design specifications are: C(s) G(s)
Kv = 20
PMd=60

70. figure(3); margin(100, [1 6 5 0]); grid; hold;
Low freq
Gain will
Give Kv=20
w=1 2 3 4

71. Problem asks for a lag lead controller
Suppose lead can make a phi-max of about 60 degrees
(1+sin(62*pi/180))/(1-sin(62*pi/180)) =16.1
(1+sin(63*pi/180))/(1-sin(63*pi/180))=17.3
Take alpha =16, rt_alp = 4.
Lag will reduce PM a little, so take wgc at a frequency where phase is just a couple deg above -180
So take wgc =2

72. Then z_lead =2/4; p_lead=2*4; Make z_lag to be 4 times below z_lead
To keep K*z_lead*z_lag/p_lag/p_lead unchanged, use p_lag = z_lag/4^2
T=1/2;a=4;margin(100*conv([T*a^2 1],[T*a 1]), conv(conv([T/a 1],[T*a^4 1]),[ ]))

73. But max phase bump is at a freq quite bit lower than wgc
Both specs are met!
But max phase bump is at a freq quite bit lower than wgc
So move all zeros and poles up by a factor of 2:
T=1/4;a=4;margin(100*conv([T*a^2 1],[T*a 1]), conv(conv([T/a 1],[T*a^4 1]),[ ]))

74. All specs are still met.
The corner frequencies are shifted to higher freq.
Phase trough and peak shifted to high freq. Phase looks better.
Wgc actually became lower.
So, which one is better?
Green or red?