1. Chapter 4 Field-Effect Transistors (FETs)
Analogue Electronics 电子 2＋2
Chapter 4 Field-Effect Transistors (FETs)

2. Ch4 – Field-Effect Transistors (FETs)
Content
4.1 Introduction
4.2 Construction and Characteristics of Junction Field-effect Transistor (JFET)
4.3 Depletion-Type MOSFET
4.4 Enhancement-Type MOSFET
4.5 Fixed-bias Configuration
4.6 Self-bias Configuration

3. Ch4 – Field-Effect Transistors (FETs)
Differences and Similarities between BJT and FET
Similarities
They are both semiconductor devices used to amplify and switch electronic signals and electrical power
Differences
The BJT transistor is a current-controlled device, whereas the FET transistor is a voltage-controlled device.

4. Ch4 – Field-Effect Transistors (FETs)
Differences and Similarities between BJT and FET
Differences
BJT transistor is a bipolar device—the prefix bi reflects the fact that there are both holes and electrons in the junctions. The conduction level is a function of two charge carriers, electrons and holes. However, the FET is a unipolar device depending solely on either electron ( n -channel) or hole ( p -channel) conduction.
FETs are more temperature stable than BJTs, and FETs are usually smaller than BJTs, making them particularly useful in integrated-circuit (IC) chips
FETs are of high input impedance with1 MΩ to several hundred megohms, it far exceeding the typical input resistance levels of the BJT transistor configurations

5. Ch4 – Field-Effect Transistors (FETs)
Types of FETs
For the FET an electric field is established by the charges present, which controls the conduction path of the output circuit without the need for direct contact between the controlling and controlled quantities.
Three types of FETs are introduced in this chapter

6. Ch4 – Field-Effect Transistors (FETs)
Construction and Characteristics of JFETs
Note that there are p-channel JFET. The major part of the p-channel JFET is the p -type material, which forms the channel between the embedded layers of n -type material. n-channel JFET is the main focus of this course.
The major part of the n-channel JFET is the n -type material, which forms the channel between the embedded layers of p -type material. The top of the n -type channel is connected through an ohmic contact to a terminal referred to as the drain (D) , whereas the lower end of the same material is connected through an ohmic contact to a terminal referred to as the source (S). The two p -type materials are connected together and to the gate (G) terminal
The source of water pressure can be likened to the applied voltage from drain to source, which establishes a flow of water (electrons) from the spigot (source). The “gate,” through an applied signal (potential), controls the flow of water (charge) to the “drain. Similarly for the JFET, we can control the electrons flowing from Source to Drain by changing the voltage between G and S.

7. Ch4 – Field-Effect Transistors (FETs)
Essential of Conductivity for JFET
Recall the current flow inside the BJT. Electrons and holes are moving towards to each via diffusion. Electrons, which are the majority carriers in the emitter, are "injected" into the base, and most of them shoot through the base into the collector. At the same time, there is a small amount of holes from collector region is “injected” into the base region, and then into the emitter region. That is why the BJT is called bipolar device.
However, for the JFET, the electrons are drawn from the source to the drain terminal, establishing the conventional current ID. In other words, only electrons participate in the current flowing. And this is the case for MOSFET and MESFET. That is why the FET is call unipolar device. IG = 0 A is an important characteristic of the JFET

8. Ch4 – Field-Effect Transistors (FETs)
For a fixed positive value of VDS, VGS is various
The voltage from gate to source, denoted VGS , is the controlling voltage of the JFET.
When VGS = 0 V.
The gate is connected directly to the source to establish the condition VGS = 0 V. The result is a gate and a source terminal at the same potential and a depletion region in p-n junctions similar to the distribution of the no-bias conditions.
What happens if a positive VDS is applied?
The instant the voltage VDD (=VDS) is applied, the electrons are drawn to the drain terminal, establishing the conventional current ID with the defined direction. And the maximum current in this case is called IDSS.

9. Ch4 – Field-Effect Transistors (FETs)
For a fixed positive value of VDS, VGS is various
When VGS < 0 V.
The gate terminal will be set at negative potential levels as compared to the source. The p-n junctions are reversed biased.
The effect of the applied negative-bias VGS is to establish wider depletion regions. This means the n-channel is thinner.
It will be more difficult for the electrons to flow through the n-channel. As a result, the current ID has been reduced.

10. Ch4 – Field-Effect Transistors (FETs)
For a fixed positive value of VDS, VGS is various
When VGS < Vp.
If VGS is made more and more negative, the depletion regions become wider and wider. Then the conductivity of the n-channel becomes smaller and smaller (the resistance of the n-channle becomes larger and larger).
If the VGS is reduced to a specified level, it will be sufficiently negative to make the depletion regions meet each other. It is like the 'door' is closed. So no current can flow through the n-channel. In other words, ID drops to 0 A.
The level of VGS that results in ID = 0 mA is defined by VP, with VP being anegative voltage. Vp is called 'turn off' voltage or 'pinch-off' voltage.

11. Ch4 – Field-Effect Transistors (FETs)
For a fixed positive value of VDS, VGS is various
An example: n-Channel JFET characteristics with IDSS = 8 mA and VP = -4 V.

12. Ch4 – Field-Effect Transistors (FETs)
For a fixed value of VGS, VDS is various (Take VGS = 0 V for example).
The JFET is conducting current at the moment. Assuming a uniform resistance in the n -channel. The current ID will establish the voltage levels through the channel.
The result is that the upper region of the p -type material will be reverse-biased by about1.5 V, with the lower region only reverse-biased by 0.5 V.
Recall from the discussion of the diode operation that the greater the applied reverse bias, the wider is the depletion region.
The depletion region is wider near the top of both p -type materials.

13. Ch4 – Field-Effect Transistors (FETs)
For a fixed value of VGS, VDS is various (Take VGS = 0 V for example).
As the voltage VDS is increased from 0 V to a few volts, the current will increase as determined by Ohm’s law and the plot of ID versus VDS will appear as shown in the left half of the figure. In this region, the resistance is essentially constant.
As VDS increases and approaches a level referred to as VP, the depletion regions will widen, causing a noticeable reduction in the channel width. The reduced path of conduction causes the resistance to increase.
If VDS is increased to a level where it appears that the two depletion regions would “touch”, a condition referred to as pinch-off will result. The level ofVDS that establishes this condition is referred to as the pinch-off voltage and is denoted by VP.

14. Ch4 – Field-Effect Transistors (FETs)
For a fixed value of VGS, VDS is various (Take VGS = 0 V for example).
In reality a very small channel still exists, with a current of very high density. So in this case, the current ID will not drop to 0 A. Instead, ID maintains a saturation level as IDSS. As VDS is increased beyond VP , the level of ID remains essentially the same.
In essence, therefore, once VDS > VP, the JFET has the characteristics of a current source.

15. Ch4 – Field-Effect Transistors (FETs)
Construction and Characteristics of JFETs
Important Conclusions for JFETs so far:
When the JFET is 'ON', the electrons flow through the n-channel from source to drain. There are no electrons or holes injected through the p-n junctions. Consequently, IG = 0 A.
When the JFET is 'ON', The conductivity is controlled by the width of the depletion regions, which is controlled by the voltages.
The width of the depletion regions is controlled by the voltage. This voltage can be VGS or VDS. And there is a pinch-off voltage Vp for both VGS and VDS.
When VGS reaches Vp, the current ID drops to 0 A. But when VDS reaches Vp, ID will not drop to 0 A. Instead, ID maintains a saturation level.

16. Ch4 – Field-Effect Transistors (FETs)
Transfer Characteristics
Now if we draw a curve along the locus of the pinch-off values, we can obtain the transfer curve of the JFET.
This indicates that the drain current ID can be controlled by the VGS. This is the common case as in reality we usually control VGS to control ID, while VDS is determined by the load circuit.

17. Ch4 – Field-Effect Transistors (FETs)
Transfer Characteristics
The above relationship between ID and VGS can also be defined by Shockley’s equation as
ID – the drain current
VGS – the voltage between gate and source. It is the control variable
VP – pinch-off voltage. The level of VGS that cause the current ID to drop to 0 A
IDSS – the maximum drain current and occurs when VGS = 0 V and VDS = |VP|.

18. Ch4 – Field-Effect Transistors (FETs)
Transfer Characteristics
When VGS = VP = -4 V, the drain current is 0 mA, defining another point on the ansfer curve. That is:

19. Ch4 – Field-Effect Transistors (FETs)
Important Relationships

20. Ch4 – Field-Effect Transistors (FETs)
Construction and Characteristics of JFETs
JFET symbols: (a) n-channel; (b) p-channel.
An easy method to distinguish the n-channel and p-channel JFETs based on the symbols:
If the drain current ID is flowing ‘in’, it is the n- ‘in’- channel JFET. Otherwise, it is the p-channel JFET.

21. Ch4 – Field-Effect Transistors (FETs)
MOSFET
The name MOSFET stands for metal-oxide-semiconductor field-effect transistor. MOSFETs are further broken down into depletion type and enhancement type. The terms depletion and enhancement define their basic mode of operation.
We focus on the depletion-type MOSFET, which has characteristics similar to those of a JFET between cutoff and saturation at IDSS, and also has the added feature of characteristics that extend into the region of opposite polarity for VGS.

22. Ch4 – Field-Effect Transistors (FETs)
n-Channel depletion-type MOSFET
Construction
A slab of p -type material is formed from a silicon base and is referred to as the substrate. It is the foundation on which the device is constructed. In some cases the substrate is internally connected to the source terminal. However, many discrete devices provide an additional terminal labeled SS, resulting in a four-terminal device. The source and drain terminals are connected through metallic contacts to n -doped regions linked by an n -channel.

23. Ch4 – Field-Effect Transistors (FETs)
n-Channel depletion-type MOSFET
Construction
The source and drain terminals are connected through metallic contacts to n -doped regions linked by an n -channel as shown in the figure. The gate is also connected to a metal contact surface but remains insulated from the n -channel by a very thin silicon dioxide (SiO2) layer.
Now the reason for the label metal–oxide–semiconductor FET is now fairly obvious: metal for the drain, source, and gate connections; oxide for the silicon dioxide insulating layer; and semiconductor for the basic structure on which the n - and p -type regions are diffused

24. Ch4 – Field-Effect Transistors (FETs)
n-Channel depletion-type MOSFET
Basic operation and characteristics (VGS = 0 V)
The gate-to-source voltage is set to 0 V by the direct connection from one terminal to the other, and a voltage VDD is applied across the drain-to-source terminals. The result is an attraction of the free electrons of the n-channel for the positive voltage at the drain. The result is a current similar to that flowing in the channel of the JFET. The resulting current with VGS = 0 V continues to be labeled IDSS

25. Ch4 – Field-Effect Transistors (FETs)
n-Channel depletion-type MOSFET
Basic operation and characteristics (VGS < 0 V)
The negative potential at the gate will tend to pressure electrons toward the p -type substrate (like charges repel) and attract holes from the p -type substrate (opposite charges attract).
Depending on the magnitude of the negative bias established by VGS , a level of recombination between electrons and holes will occur that will reduce the number of free electrons in the n -channel available for conduction.
The more negative the bias, the higher is the rate of recombination. The resulting level of drain current is therefore reduced with increasing negative bias for VGS ,

26. Ch4 – Field-Effect Transistors (FETs)
n-Channel depletion-type MOSFET
Basic operation and characteristics (VGS > 0 V)
For positive values of VGS, the positive gate will draw additional electrons (free carriers) from the p-type substrate due to the reverse leakage current and establish new carriers through the collisions resulting between accelerating particles. As the gate-to-source voltage continues to increase in the positive direction, the drain current will increase at a rapid rate.

27. Ch4 – Field-Effect Transistors (FETs)
n-Channel depletion-type MOSFET
It has characteristics similar to those of a JFET between cutoff and saturation at IDSS , and also has the added feature of characteristics that extend into the region of opposite polarity for VGS
The application of a positive gate-to-source voltage has “enhanced” the level of free carriers in the channel compared to that encountered with VGS > 0 V. For this reason the region of positive gate voltages on the drain or transfer characteristics is often referred to as the enhancement region , with the region between cutoff and the saturation level of IDSS referred to as the depletion region.
Shockley’s equation will continue to be applicable for the depletion-type MOSFET characteristics in both the depletion and enhancement regions.

28. Ch4 – Field-Effect Transistors (FETs)
Depletion-type MOSFET
n-channel
p-channel
Note how the symbols chosen try to reflect the actual construction of the device. The lack of a direct connection (due to the gate insulation) between the gate and the channel is represented by a space between the gate and the other terminals of the symbol. The vertical line representing the channel is connected between the drain and the source and is “supported” by the substrate.

29. Ch4 – Field-Effect Transistors (FETs)
n-Channel enhancement-Type MOSFET
Construction
A slab of p -type material is formed from a silicon base and is again referred to as the substrate.
The source and drain terminals are again connected through metallic contacts to n -doped regions, but note the absence of a channel between the two n -doped regions. This is the primary difference between the construction of depletion-type and enhancement-type MOSFETs.
The SiO2 layer is still present to isolate the gate metallic platform from the region between the drain and source, but now it is simply separated from a section of the p -type material

30. Ch4 – Field-Effect Transistors (FETs)
n-Channel enhancement-Type MOSFET
When VGS = 0 V and VDS > 0 V.
If VGS is set at 0 V and a voltage applied between the drain and the source of the device, the absence of an n -channel (with its generous number of free carriers) will result in a current of effectively 0 A—quite different from the depletion-type MOSFET and JFET, where ID = IDSS. It is not sufficient to have a large accumulation of carriers (electrons) at the drain and the source (due to the n -doped regions) if a path fails to exist between the two.

31. Ch4 – Field-Effect Transistors (FETs)
n-Channel Enhancement-Type MOSFET
When VGS > 0 V and VDS > 0 V.
Both V D S and V GS have been set at some positive voltage greater than 0 V, establishing the drain and the gate at a positive potential with respect to the source.
The positive potential at the gate will pressure the holes (since like charges repel) in the p -substrate along the edge of the SiO2 layer to leave the area and enter deeper regions of the p -substrate.
At the same time, the electrons in the p -substrate (the minority carriers of the material) will be attracted to the positive gate and accumulate in the region near the surface of the SiO2 layer.
As VGS increases in magnitude, the concentration of electrons near the SiO2 surface increases until eventually the induced n -type region can support a measurable flow between drain and source.
The level of VGS that results in the significant increase in drain current is called the threshold voltage and is given the symbol VT .

32. Ch4 – Field-Effect Transistors (FETs)
n-Channel Enhancement-Type MOSFET
When VGS > 0 V and VDS > 0 V.
Based on the above analysis, it can be seen that since the channel is nonexistent with VGS = 0 V. The induced channel is created by applying VGS > 0 V. In other words, the device is “enhanced” by the application of a positive gate-to-source voltage, so this type of MOSFET is called an enhancement-type MOSFET
The term “enhancement” in enhancement-type MOSFET and the term “enhancement” in enhancement region are different.
Enhancement-type MOSFET means the positive VGS is required to create or enhance the conducting channel. This kind of MOSFET can only operate when VGS > 0 V.
For depletion- type MOSFETs, they have depletion regions and enhancement-type regions. They operate in depletion regions when VGS < 0 V and enhancement regions when VGS > 0 V

33. Ch4 – Field-Effect Transistors (FETs)
n-Channel Enhancement-Type MOSFET
Saturation
As VGS is increased beyond the threshold level, the density of free carriers in the induced channel will increase, resulting in an increased level of drain current. However, if we hold VGS constant and increase the level of VDS, the drain current will eventually reach a saturation level as occurred for the JFET and depletion-type MOSFET. The leveling off of ID is due to a pinching-off process depicted by the narrower channel at the drain end of the induced channel

34. Ch4 – Field-Effect Transistors (FETs)
n-Channel Enhancement-Type MOSFET
Transfer Characteristics
To sum up, we have
For values of VGS less than the threshold level, the drain current of an enhancement type MOSFET is 0 mA.
For levels of VGS > VT, the drain current is related to the applied gate-to-source voltage by the following nonlinear relationship

35. Ch4 – Field-Effect Transistors (FETs)
First thing you need to know
We have performed the dc analysis and ac analysis for BJTs. Most of the methods and theory for BJT circuits can be employed for FET circuits.

36. Ch4 – Field-Effect Transistors (FETs)
Introduction
The general relationships that can be applied to the dc analysis of all FET amplifiers are
For JFETs and depletion-type MOSFETs and MESFETs, Shockley’s equation is applied to relate the input and output quantities
For enhancement-type MOSFETs, the following equation is applicable

37. Ch4 – Field-Effect Transistors (FETs)
Fixed-bias configuration
Determine the following for the network
a. VGSQ.
b. IDQ.
c. VDS.
d. VD.
e. VG.
f. VS.
For the dc analysis
The zero-volt drop across RG permits replacing RG by a short-circuit equivalent
Applying Kirchhoff’s voltage law in the clockwise direction of the indicated loop
Since VGG is a fixed dc supply, the voltage VGS is fixed in magnitude, resulting in the designation fixed-bias configuration.

38. Ch4 – Field-Effect Transistors (FETs)
Fixed-bias configuration - Mathematical Approach
The resulting level of drain current ID is now computed by Shockley’s equation
Applying Kirchhoff’s voltage law from VDD to the earth

39. Ch4 – Field-Effect Transistors (FETs)
Fixed-bias configuration - Graphical Approach
A graphical analysis would require a plot of Shockley’s equation.
To draw this curve, at least three points are required: Two intersection points and the point (VGS = VP/2 , ID = IDSS/4)
Plot the vertical line at VGS = -2 V
From the graph, we find that

40. Ch4 – Field-Effect Transistors (FETs)
Fixed-bias configuration - Graphical Approach
After IDQ is determined, the other parameters can be calculated similarly as before

41. Ch4 – Field-Effect Transistors (FETs)
Self-bias configuration
Determine the following for the network
a. VGSQ.
b. IDQ.
c. VDS.
d. VS.
e. VG.
f. VD.
Again, the resistor RG replaced by a short-circuit equivalent since IG = 0 A.
The current through RS is the source current IS, and IS = ID, so
Apply KVL at the indicated loop
(2)
(1)
Note that VGS is a function of the output current ID and RS and not fixed in magnitude as occurred for the fixed-bias configuration. It is defined by the network configuration, and Shockley’s equation relates the input and output quantities of the device. Both equations relate the same two variables, ID and VGS.

42. Ch4 – Field-Effect Transistors (FETs)
Self-bias configuration - Mathematical Approach
(1)
(2)
A mathematical solution could be obtained simply by substituting (1) into (2) as follows:
IDQ
After that, other parameters can be determined using basic circuit theory

43. Ch4 – Field-Effect Transistors (FETs)
Self-bias configuration - Graphical Approach
(1)
(2)
Two equations result in two lines. The intersection point of these two curves are the operating point of the FET circuit.
First draw the curve of Shockley’s equation by identifying three points, as explained early.
Next, draw the curve of (1) by identifying two points. One point on the straight line is defined by ID = 0 A and VGS = 0 V. Then we can choose another point at (ID = IDSS/2, VGS = -IDRS = -IDSSRS/2)
Choosing ID = 4 mA, we obtain

44. Ch4 – Field-Effect Transistors (FETs)
Self-bias configuration - Graphical Approach
Plot the previous two lines together, one can obtain
Based on this graph, the operating point can be found as
Once again, other parameters can be determined using basic circuit theory afterwards.

45. Ch4 – Field-Effect Transistors (FETs)
In-class test
For the fixed-bias configuration. determine:
a. IDQ and VGSQ using a purely mathematical approach.
b. Repeat part (a) using a graphical approach and compare results.
c. Find VDS, VD, VG, and VS using the results of part (a).

46. Ch4 – Field-Effect Transistors (FETs)
Voltage-Divider Biasing
Determine the following for this JFET network:

47. Ch4 – Field-Effect Transistors (FETs)
Voltage-Divider Biasing
Hint:
The variables such as VD, VS, VDS can be calculated if ID is determined. Since IG = 0 A, ID = IS. the key is to find IS.
In order to find IS, we can apply KVL to the indicated loop. This can provide a link between VGS and IS. In other words, an equation including VGS and ID can be obtained.
Because IDSS and Vp are known, the JFET transfer characteristics (the Shockley’s equation) can be determined.
The results are two equations with two variables VGS and ID.

48. Ch4 – Field-Effect Transistors (FETs)
Voltage-Divider Biasing
Apply KVL at the indicated loop
and
substituting
(1)

49. Ch4 – Field-Effect Transistors (FETs)
Voltage-Divider Biasing
The transfer characteristics, i.e., the Shockley’s equation can then be written as
(2)
Now ID and VGS can be calculated using either the methematical method or the graphical method
For methematical method, combining (1) and (2) results in IDQ

50. Ch4 – Field-Effect Transistors (FETs)
Voltage-Divider Biasing
For the graphical method, we need to plot the curives of (1) and (2), respectively.
For equation (1), two points are required. When ID = 0 mA,
When VGS = 0 V,
For equation (2), three points are required. when ID = 0,
VGS = - 4 V.
when VGS = 0,

51. Ch4 – Field-Effect Transistors (FETs)
Voltage-Divider Biasing
When VGS = VP/2 = -2 V, ID = IDSS/4 = 2 mA.

52. Ch4 – Field-Effect Transistors (FETs)
Voltage-Divider Biasing

53. Ch4 – Field-Effect Transistors (FETs)
Common-gate configuration
Determine the following for the common-gate configuration.
a. VGSQ
b. IDQ
c. VD
d. VG
e. VS
f. VDS
For this equation the origin is one point on the load line. For the other point, choosing ID = 6 mA and solving for V GS will result in the following
To plot the transfer characteristics, three points are required. When ID = 0,
VGS = -6 V.
when VGS = 0,
When VGS = VP/2 = -3 V, ID = IDSS/4 = 3 mA.

54. Ch4 – Field-Effect Transistors (FETs)
Common-gate configuration
Determine the following for the common-gate configuration.
a. VGSQ
b. IDQ
c. VD
d. VG
e. VS
f. VDS
Plot two curves on one graph and the intersection point is

55. Ch4 – Field-Effect Transistors (FETs)
Common-gate configuration
Determine the following for the common-gate configuration.
a. VGSQ
b. IDQ
c. VD
d. VG
e. VS
f. VDS

56. Ch4 – Field-Effect Transistors (FETs)
Combination Networks
Determine the levels of V D and V C for the network
It is a network inlcuding JFET and BJT. Take an in-dept investigation, it can be found that it is actually a BJT based voltage-divider circuit.

57. Ch4 – Field-Effect Transistors (FETs)
Combination Networks
Determine the levels of V D and V C for the network

58. Ch4 – Field-Effect Transistors (FETs)
Combination Networks
A more careful examination reveals that VC is linked to VB by VGS. IG = 0 A, RG can be "short-circuit". Therefore
The question then arises as to how to find the level of VGSQ
From the Shockley’s equation, we have
VGSQ could be found mathematically by solving for VGSQ as

59. Ch4 – Field-Effect Transistors (FETs)
n-Channel Depletion-type MOSFETs
For the n-channel depletion-type MOSFET, VGS can be smaller than zero and larger greater than zero. The transfer characteristics present both depletion region and enhancement region.

60. Ch4 – Field-Effect Transistors (FETs)
n-Channel Depletion-type MOSFETs
Setting ID = 0 mA results in
Setting VGS = 0 V yields
To plot the transfer characteristics clearly, four points are required. Two intersection points can be easly identified as (-3, 0) and (0, 6).
The third point can be chosen as VGS = VP/2 = -1.5 V, ID = IDSS/4 = 1.5 mA.
The fourth point can be chosen as VGS = + 1 V, and

61. Ch4 – Field-Effect Transistors (FETs)
n-Channel Depletion-type MOSFETs
Plot these two curves at one figure. The resulting operating point is given by

62. Ch4 – Field-Effect Transistors (FETs)
n-Channel Enhancement-type MOSFETs
Determine IDQ and VDSQ for the enhancement-type MOSFET
For the n -channel enhancement-type MOSFET, the drain current is zero for levels of gate-to-source voltage less than the threshold level VGS(Th). For levels of V GS greater than VGS(Th), the drain current is defined by

63. Ch4 – Field-Effect Transistors (FETs)
n-Channel Enhancement-type MOSFETs
For VGS = 6 V (between 3 and 8 V):
For VGS = 10 V (slightly greater than VGS(Th)):
The other two ponts are (3, 0) and (8, 6). Now four points are sufficient to plot the full curve

64. Ch4 – Field-Effect Transistors (FETs)
n-Channel Enhancement-type MOSFETs
Now four points are sufficient to plot the full curve

65. Ch4 – Field-Effect Transistors (FETs)
n-Channel Enhancement-type MOSFETs

66. Ch4 – Field-Effect Transistors (FETs)
In-class test
For the voltage-divider configuration , determine:
a. IDQ and VGSQ.
b. VD and VS .

67. Ch4 – Field-Effect Transistors (FETs)
Practical Applications - Voltage-Controlled Resistor (Noninverting Amplifier)
Three types of FETs are introduced in this chapter: the junction field-effect transistor
(JFET), the metal–oxide–semiconductor field-effect transistor (MOSFET), and the metal –semiconductor field-effect transistor (MESFET). The MOSFET category is further broken down into depletion and enhancement types, which are both described.

68. Ch4 – Field-Effect Transistors (FETs)
Practical Applications - Timer Network
Three types of FETs are introduced in this chapter: the junction field-effect transistor
(JFET), the metal–oxide–semiconductor field-effect transistor (MOSFET), and the metal –semiconductor field-effect transistor (MESFET). The MOSFET category is further broken down into depletion and enhancement types, which are both described.

69. Ch4 – Field-Effect Transistors (FETs)
Practical Applications - Fiber Optic Systems
Three types of FETs are introduced in this chapter: the junction field-effect transistor
(JFET), the metal–oxide–semiconductor field-effect transistor (MOSFET), and the metal –semiconductor field-effect transistor (MESFET). The MOSFET category is further broken down into depletion and enhancement types, which are both described.

70. Ch4 – Field-Effect Transistors (FETs)
Practical Applications - MOSFET Relay Driver
Three types of FETs are introduced in this chapter: the junction field-effect transistor
(JFET), the metal–oxide–semiconductor field-effect transistor (MOSFET), and the metal –semiconductor field-effect transistor (MESFET). The MOSFET category is further broken down into depletion and enhancement types, which are both described.