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Directory-based Protocol

Published byΞένα Παπαδάκης Modified over 6 years ago

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Presentation on theme: "Directory-based Protocol"— Presentation transcript:

1 Directory-based Protocol
Interconnection Network Directory Local Memory Cache CPU 0 CPU 1 CPU 2

2 Directory-based Protocol
Interconnection Network CPU 0 CPU 1 CPU 2 Bit Vector X U 0 0 0 Directories X 7 Memories Caches

3 Interconnection Network
CPU 0 Reads X Interconnection Network Read Miss CPU 0 CPU 1 CPU 2 X U 0 0 0 Directories X 7 Memories Caches

4 Interconnection Network
CPU 0 Reads X Interconnection Network CPU 0 CPU 1 CPU 2 X S 1 0 0 Directories X 7 Memories Caches

5 Interconnection Network
CPU 0 Reads X Interconnection Network 7 X CPU 0 CPU 1 CPU 2 X S 1 0 0 Directories 7 X Memories Caches

6 Interconnection Network
CPU 2 Reads X Interconnection Network CPU 0 CPU 1 CPU 2 X S 1 0 0 Directories Read Miss 7 X Memories Caches 7 X

7 Interconnection Network
CPU 2 Reads X Interconnection Network CPU 0 CPU 1 CPU 2 X S 1 0 1 Directories 7 X Memories Caches 7 X

8 Interconnection Network
CPU 2 Reads X Interconnection Network CPU 0 CPU 1 CPU 2 X S 1 0 1 Directories 7 X Memories 7 X Caches 7 X

9 Interconnection Network
CPU 0 Writes 6 to X Interconnection Network CPU 0 Write Miss CPU 1 CPU 2 X S 1 0 1 Directories 7 X Memories Caches 7 X 7 X

10 Interconnection Network
CPU 0 Writes 6 to X Interconnection Network CPU 0 CPU 1 CPU 2 X S 1 0 1 Directories Invalidate 7 X Memories Caches 7 X 7 X

11 Interconnection Network
CPU 0 Writes 6 to X Interconnection Network CPU 0 CPU 1 CPU 2 X E 1 0 0 Directories 7 X Memories Caches X 6

12 Interconnection Network
CPU 1 Reads X Interconnection Network CPU 0 CPU 1 Read Miss CPU 2 X E 1 0 0 Directories 7 X Memories Caches 6 X

13 Interconnection Network
CPU 1 Reads X Interconnection Network CPU 0 Switch to Shared CPU 1 CPU 2 X E 1 0 0 Directories 7 X Memories Caches 6 X

14 Interconnection Network
CPU 1 Reads X Interconnection Network CPU 0 CPU 1 CPU 2 X E 1 0 0 Directories 6 X Memories Caches 6 X

15 Interconnection Network
CPU 1 Reads X Interconnection Network CPU 0 CPU 1 CPU 2 X S 1 1 0 Directories 6 X Memories Caches 6 X 6 X

16 Interconnection Network
CPU 2 Writes 5 to X Interconnection Network CPU 0 CPU 1 CPU 2 X S 1 1 0 Directories 6 X Memories Write Miss Caches 6 X 6 X

17 Interconnection Network
CPU 2 Writes 5 to X Interconnection Network CPU 0 Invalidate CPU 1 CPU 2 X S 1 1 0 Directories 6 X Memories Caches 6 X 6 X

18 Interconnection Network
CPU 2 Writes 5 to X Interconnection Network CPU 0 CPU 1 CPU 2 X E 0 0 1 Directories 6 X Memories X 5 Caches

19 Interconnection Network
CPU 0 Writes 4 to X Interconnection Network Write Miss CPU 0 CPU 1 CPU 2 X E 0 0 1 Directories 6 X Memories 5 X Caches

20 Interconnection Network
CPU 0 Writes 4 to X Interconnection Network CPU 0 CPU 1 CPU 2 X E 1 0 0 Directories 6 X Memories Take Away 5 X Caches

21 Interconnection Network
CPU 0 Writes 4 to X Interconnection Network CPU 0 CPU 1 CPU 2 X E 0 1 0 Directories 5 X Memories 5 X Caches

22 Interconnection Network
CPU 0 Writes 4 to X Interconnection Network CPU 0 CPU 1 CPU 2 X E 1 0 0 Directories 5 X Memories Caches

23 Interconnection Network
CPU 0 Writes 4 to X Interconnection Network CPU 0 CPU 1 CPU 2 X E 1 0 0 Directories 5 X Memories Caches 5 X

24 Interconnection Network
CPU 0 Writes 4 to X Interconnection Network CPU 0 CPU 1 CPU 2 X E 1 0 0 Directories 5 X Memories Caches X 4

25 Interconnection Network
CPU 0 Writes Back X Block Interconnection Network CPU 0 Data Write Back CPU 1 CPU 2 X E 1 0 0 Directories 4 X 5 X Memories Caches 4 X

26 Interconnection Network
CPU 0 Writes Back X Block Interconnection Network CPU 0 CPU 1 CPU 2 X U 0 0 0 Directories 4 X Memories Caches

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