1. Synthesis for Verification
Alan Mishchenko
UC Berkeley

2. Overview Introduction Motivation Synthesis for Summary CEC Induction
etc
Summary

3. Introduction What to do if an EC or MC problem is too hard?
Run SAT solver for hours, hoping it magically solves it
This may not be the best use of time
There may be other, more effective things to try
One possibility is to use synthesis
The focus of this presentation is on how to ease verification problems using synthesis

4. Motivation
A heavy-duty Boolean resynthesis can reduce area 5x, while the standard synthesis reduces only 5%!
A. Mishchenko, R. Brayton, J.-H. R. Jiang, and S. Jang, "SAT-based logic optimization and resynthesis". Rejected by ICCAD and FPGA => good paper 

5. Discussion These circuits are derived from PLAs
Circuit structure is highly suboptimal
Standard synthesis cannot overcome the structural bias
SAT-based Boolean resubstitution with don’t-cares is needed
Unsatisfiable sequential miters typically have almost all states unreachable
These states can be used to restructure the circuit
Efficient methods are needed
To compute subsets of unreachable states
To globally re-synthesize circuit structure

6. Synthesis for CEC Infamous example
Two multipliers with different logic structure
No internal equivalent points
Both BDD construction and SAT sweeping fail!

7. Synthesis for CEC
If there is no internal equivalences, synthesize them! A B
New equivalence: A = B

8. Synthesis for Induction
Achilles' heel of induction: Inductiveness leaks
Unreachable states creating spurious counter-examples
Remedy: Strengthening induction
Excluding leaks by adding new properties to be checked
reachable
unreachable P

9. Previous Work Fixing inductiveness leaks Van Eijk’s approach (TCAD’00)
Use candidate equivalences
If not enough, add dangling nodes (nodes after retiming)
Mike Case’s approach (FMCAD’07)
Use implications that cover counter-examples
Aaron Bradley’s approach (FMCAD’07)
Use minimal clauses derive from counter-examples
New approach
Synthesize new logic cones

10. Synthesis for Induction
If we cannot prove P, our goal is to synthesize a new cone Q that strengthens P n P Q Y X

11. Synthesis for Induction
Perform two simulations:
Combinational (C)
Sequential (S)
Collect patterns in Y-space of n appearing in C but not in S
These are due to unreachable states
OR these patterns to get Q(y)
Q(y) is a candidate property that is true in all reachable states
Consider 4-input cuts of all nodes n P Q Y X

12. Summary Synthesis and verification go hand in hand
When one gets stuck, the other comes to rescue
How to use synthesis to help verification?
This presentation outlined several ideas
This is a promising direction of future work