1. ESD Protection for Ultra High Voltage (200V) BCD SOI Platform
Roda Kanawati, Efraim Aharoni, Avi Parvin,
Allon Parag, Olivier Bansay, Moran Cohen Yasour - TowerJazz
Katsuya Arai, Shun Kano - TowerJazz Panasonic Semiconductor Corporation (TPSCo)
May 1, 2018

2. Outline ESD Window and ESD protection motivation
Ultra High Voltage (200V) BCD SOI platform introduction
UHV BCD SOI – ESD perspective and challenges
200V ESD protection scheme
Low Voltage (CMOS) protection and I/O library
Middle Voltage and UHV protection
Summary and conclusions

3. ESD Motivation - Reminder
On-chip ESD Protection (at IC level), should provide protection to the IC from ESD discharge during IC handling, packaging, and use
Main ESD models/ratings (at IC/package level)
Human Body Model (HBM) / 2000V
Machine Model (MM) / 200V
Charge Device Model / 500V

4. ESD Protection Requirements
Clamp the ESD voltage to shunt the ESD stress current
Turn on fast (less than 1ns)
Carry large currents of ~2 A or more for ~150ns
Have low on-resistance
Occupy minimum area at bond pad
Have minimum capacitance and series resistance
Immune to process drifts
Robust for numerous pulses
Offer protection for various ESD stress models
Not interfere with the IC functionality
Not cause increased Vcc or IO leakage
Survive the burn-in tests
ESD Design Window

5. UHV (200V) BCD SOI platform
(Bulk) 0.18m PM BCD (Bipolar CMOS/DMOS)
Combines 1.8V/5V (LV) CMOS, analog components, and Medium Voltage (<60V operation) transistors with low on-resistance, in a single chip
Suppressing carriers injection to the substrate by enhanced junction isolation and ‘Resurf’ technology
Disadvantages: 1. Potential triggering of parasitic devices and L/U prevention overall efficiency due to injections. 2. Voltage ranges are limited to tens of Volts. 3. Junction isolation limits temperature range
PM BCD in SOI combined with Deep Trench (DT), uses SiO2 to selectively isolate chip elements
Effective suppression of carriers injection
Allows smaller chip area (especially of higher voltages operation)
Supports higher voltages (200V typical BV)

6. 0.18m PM Isolation Options
Base Isolation: (LED, DC/DC)
Cost Effective solution for high Voltage low current applications (<1.5A)
Cost
Shallow Epi: (DC/DC, Motors, POE)
Blocks Hole injection in HC applications
Medium to large current applications (2~8A)
Deep Epi: (AMOLED, POLs)
Blocks hole & Electron injections
Negative bias
SOI: (High Voltage, High Current)
Superb Isolation, high voltage
Dense isolation rules
Isolation

7. 200V BCD SOI platform introduction
Features
Applications
Extends voltage capabilities
Noise and LatchUp immunity
Fully isolated transistor
Negative voltage operation
Area reduction (dense isolation rules)
Low leakage
Fast reverse recovery
SPICE compatibility with 0.18m bulk process
Motor controllers
Medical (multi Channel)
Automotive
High immunity to
ESD/EMC & Latchup
EV Battery Gauge
Home Appliances & Industrial
(AC/DC converters, motor drivers,
and Power over Ethernet.)

8. UHV SOI BCD – ESD Perspective
HV (200V) BCD:
Requires UHV (200V) ESD devices; High breakdown voltage, high IV power, narrow ESD design window
Challenging integration of ESD protection; multiple domains (HV, MV, LV), floating devices/circuits, multiple clamp ranges.
SOI (and DT):
Floating body and snapback performance degradation (in case of FD bulk)
Thermal effects (self-heating)
Reduced Latch-Up and triggering of parasitic devices

9. 200V SOI ESD Protection
LV (1.8V/5V) and MV (<60V ldmos) ESD protection is similar to bulk BCD protection, except for effects caused by the SOI/DT isolation
HV ESD protection is based on stacking MV SCR (Silicon Controlled Rectifier) devices for positive stress and a HV ESD diode for negative stress

10. 200V ESD Protection Scheme

11. Low Voltage Protection
Due to the thick EPI layer - No significant differences in LV ESD Devices snapback characteristics (except Ron)
Employ similar protection circuits
Systematic increase of Ron (after ESD transistor snapback) due to self heating  Requires update of electronic DR (total width)
Ron of 5V ESD NMOS
transistor (after snapback)

12. I/O Library Modification
Added DT ring
Nwell
‘No Pwell’
Modified GDS and CDL, based on existing library (keeping library features, and ease development)
junction isolation left and used to generate DT
Adding SOI-related parasitic capacitors (for scheme simulation and LVS)
DRC and LVS
Next phase may reduce area (no need of guard-rings)
Original IO cell
After modification

13. MV ESD Devicess
CGNLDMOS – RC coupled active clamp (no snapback), can be simulated
MV ESD coupling diodes
Scalable SCR - Voltage triggered solution (snapback)
CGNLDMOS
SCR
ESD Diode (w/ DT)

14. CGNLDMOS Simulation
Simulation success criteria – handling the required ESD rating within the device normal operating conditions; Vds≤Vdd, Vgs≤5V
Example – 2.5kV HBM stress over an 42V clamp
Vds<42V, Vgs<5V
Ids1.6A
(2.5kV HBM equivalent) I
Vgs
Vds

15. Scalable SCR TLP Data

16. HV Diodes
Reverse bias DC
Forward bias TLP

17. HV Clamp – Stacked SCR NLDMOS-based SCR
Based on the core device, hence if the core BV shifts, the SCR BV/Vt1 will shift at the same direction! Process variation effects are reduced
Stacked SCR properties are defined by single SCR scaling parameter and number of stacked SCR devices
Stacked SCR DC BV higher > abs max voltage (with some margin for process and temp. variation)
Vt1 < LDMOS BV

18. Stacked SCR TLP Characteristics
Excellent it2 results, do not drop with increasing number of Stacked SCR’s

19. Stacked SCR DC CharacteristicsBV
DC BV mechanism seems to be punch-through and not avalanche (Abrupt leakage change)

20. Stacked SCR Scalability

21. Summary and Conclusions
LV and MV bulk BCD ESD solutions (devices, protection circuits, 1.8V/5V I/O library) can be used in 200V SOI platform with minor modifications
ESD devices successfully developed to answer up to 200V operation voltage
Si proven protection scheme integrating LV, MV, and HV (200V) devices/circuits successfully developed
Since the SCR (in the 200V ESD clamp) is LDMOS based, the core device and SCR share the same break-down mechanism, and the ESD window can be narrowed