1. A Step-By-Step Description of the System Generator Flow
Section A
A Step-By-Step Description of
the System Generator Flow
For a Colour Space Convertor
In this section, a colour image stored as a bit map file is converted into 3 files containing pixel data for each of the primaries Red, Green and Blue. A script executed in the Matlab domain is used to create these files in the Matlab Workspace
These separate files can then be accessed by a Simulink block diagram, which describes the structure of the RGB2YPBPR convertor of Figure 25.
The Simulink model contains both an RGB2YPBPR and YPBPR2RGB convertor core, so in addition to being able to review the monochrome YPBPR outputs, we can also review the output of the YPBPR2RGB convertor core as a reconstructed bitmap.
This exercise also identifies the need to have prior knowledge of the latency of the cores being used in the Simulink domain; this is easily obtainable from CORE Generator, but it demonstrates that you cannot be totally ignorant of the hardware implementation.
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2. System Generator Flow - Source Image
362 lines
500 rows
500 pixels/row x 362 rows = pixels = Million bits
(24-bit colour). Each pixel = 8-bit Red + 8-bit Green + 8-bit Blue
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3. SysGen Flow - Start New Project1
Start Matlab, and then Simulink
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4. SysGen Flow - Open Simulink Project
Red, Green and Blue
pixel data are loaded
from variables in the
Matlab Workspace
Use a Z-1 token to imply a register.
A single register next to the inputs and outputs
of the Xilinx domain will get mapped to the
IOBs of the device. This will reduce the clock
to setup and clock to out times of the FPGA.
(i.e., data bandwidth increases.)
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5. SysGen Flow - RGB2YPBPR core
Note the use of CORE Generator Full multipliers with a
constant input! This is None Optimal use of the
device, as one input of the mutiplier is constant.
A Constant Coefficient Multiplier should be used;
however, at present, the CORE Generator Constant
Coefficient Multiplier is not supported by the System
Generator. It was decided to use the full multipliers
to demonstrate the Smart-IP design advantages.
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6. SysGen Flow - Setup Workspace
This Matlab script is used to set up variables in the Matlab
workspace. This script scans each pixel of the picture,
splitting it into three separate arrays of Red, Green and
Blue data.
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7. SysGen Flow - Set up Workspace
Execute the PreProc_flowers.m script
to set up Matlab workspace.
Notice how the variables appear in the
Workspace viewer.
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8. SysGen Flow - Run the Simulation
Having set up the source and destination variables in the
Matlab workspace, the simulation can be started.
Be prepared to wait a while as it works its way through a
lot of data!……. And consider that this is just a single
frame. Any temporal processing that requires multiple
frames may require considerable time to process.
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9. Run a Post-Processing Script
Now run a second script to perform two tasks:
1) Create images of the separate Y Cb Cr outputs;
2) Read the RGB outputs from the YPbPr2RGB convertor and see if the picture that has been
converted from RGB to YPbPr and back to RGB has any visible differences from the original.
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10. SysGen Flow - View the Output
Execute the PostProc_flowers.m script to display the Luma and Colour difference
channels as images; also, display the reconstructed images.
(All RGB2YPBPR channels viewed as monochrome signals.) PB PR Y
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11. SysGen Flow - Check the Results
Picture In
Picture Out,
… Oh dear!
Something has clearly gone wrong, either in one or both of the conversions; the colours are clearly skewed within this image.
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12. - Remember to balance latency!
Note how the delays are not
balanced because we forgot
to add delay to this mutliplier.
Z-5
Beware! At present, you must add the correct
silicon latency to the cores via their masks,
because this information isn’t characterized
into the current Simulink models.
Z-2
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13. SysGen Flow - Corrected output
Picture In
Picture Out -
this is better!
The pipeline delays are now
balanced, and the image is
reconstructed correctly, as the
Y, PB and PR components are
all associated with the same pixel.
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14. SysGen Flow - Export VHDL Files
Double-click on this icon to set up
the System Generator options...
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15. SysGen Flow - SysGen Token GUI
Select your target
technology:
- Virtex
- Virtex-II
- Spartan-II
Select a target
directory for all the
System Generator:
-EDIFs
-VHDs
-TestBenches
-Data files
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16. SysGen Flow - Generating The Files
Generate the output files
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17. SysGen Flow - Successful
Process Completed.
All output files are now written in
the target directory and the next stage of the
flow can take place...synthesis!
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(Press your “Page Down”
key to end the presentation.)