1. SEE Characterization of XC7K70T, Kintex Serie7 familly FPGA from Xilinx
Hello everyone, I’m ELG, I’m here today to present you a SEE ch…, performed at RADEF, Finland.
Work performed by Enoal LE GOULVEN, Pierre GARCIA, Alexandre ROUSSET, Athina VAROTSOU (TRAD)
Marc POIZAT, David MERODIO CODINACHS, Thomas LANGE (ESA)
ESA Contract No : /15/NL/RA/gp
ESA / CNES March 2017

2. Outline Aim of this study SEE testing Conclusion Device description
Beam description
Test bench overview
For each design tested
Test method
Test results
Conclusion
I’ll start to present the device description, I will talk about the beam use for this test, test bench overview and for each design, a description of test method and test results.
A conclusion will wrap-up this presentation.
ESA / CNES March 2017

3. PARTS PROCUREMENT INFORMATIONS
Aim of this study
The aim of this study is to test a new technology of FPGA (28nm) in Latch Up, Upset and Functional Interrupt under Heavy Ions beam.
PART IDENTIFICATION
Type :
XC7K70T
Manufacturer :
Xilinx
Node:
28nm
Function :
FPGA
PARTS PROCUREMENT INFORMATIONS
Packaging :
BGA484  Flip-chip !
The aim is to study the 28nm Xilinx FPGA technology under heavy ions. The tested reference is a commercial version of the Kintex-7 family.
ESA / CNES March 2017

4. Component preparation
TOP
Flip chip die
Die directly interfaced on the PCB package
Reduce thickness of the die
Range to reach the active zone ≈ 60µm
XC7K70T-1FBG484C-Cross-section
Around 700µm of silicium was removed in order to reach the active zone under the heavy ion beam.
Active zone of the die
Metallic ball
ESA / CNES March 2017

5. Beam description : RADEF
Energie
(MeV)
Range
(µm(Si))
LET
(MeV.cm².mg-1)
15N+4
139
202
1.83
20Ne+6
186
146
3.63
40Ar+12
372
1118
10.2
56Fe+15
523 97
18.5
84Kr+22
768 94
32.2
131Xe+35
1217 89 60
RADEF, Finland
Beam time : 20h
Active zone is at approximately 60µm.
Xenon range from 89µm
RADEF facility validated for this test
We have used the beam facility of RADEF in Finland for a high range.
The heavy ion cockatils is available in yellow in this table.
ESA / CNES March 2017

6. Test Bench - Hardware VIRTEX4 ESA / CNES March 2017 USB GUARD SYSTEM
configuration
and
output
signals
PC for storage and
visualisation
USB
GUARD SYSTEM
GPIB IEEE488
Power
Supply
Signals
SEL Curves
Current
Consumption
FPGA Board
high end modular power supply
DUT
test
test
The test bench consist of an oscilloscope, a GUARD system which is an anti latch-up kit, a BILT power supply, a Virtex-4 FPGA board, DUT test board and a laptop.
The FPGA board is used to affect the inputs and to detect all errors on the outputs of the application software implemented in the DUT.
VIRTEX4
ESA / CNES March 2017

7. Test Bench – At a glance Single Event Latch Up (SEL)
Temperature : +85°C
Fluence : 1E7 #/cm2
14 power supplies monitored :
- 2 Guard System  Latch Up detection
- BILT  Current monitoring during irradiation
- For each power supply  Compliance at 1A
Single Event Upset and Functional Interrupt (SEFI)
Temperature : Ambiant
Fluence : 1E6 #/cm2
3 test designs and results
The main information here are the SEL power supply monitoring. 2 GUARD systems are used for latch-up detection, a BILT is used for curent monitoring during irradiation, and for ech power supply, the maximum compliance is 1A.
Test charactics are shown in this slide.
ESA / CNES March 2017

8. Single Event Latchup : Test Results
No SEL was observed
BUT current increased on VCCAUX, VCCINT, VCCBRAM, MGTAVCC, VCCCO_13, VCCO_15, VCCO_33 until compliance (1A)
No SEL was detected during the irradiation but, depending on the flux, an increase of current has been observed up to the power supplies compliance. In this case 1A.
ESA / CNES March 2017

9. Single Event Upset and Functional Interrupt
Three different designs:
Shift Registers
Block Memory
32-bit Counter, developed and provided by Thomas Lange and David Merodio Codinachs from ESA
Three designs were developed in order to characterize the different FPGA elements.
For the first design 9 chains of shift registers has been used
For the second one, a block memory has been used
And for the last one, a design developed by ESA used several 32-bit counters
ESA / CNES March 2017

10. Single Event Upset and Functional Interrupt
Design 1 : Shift register chain
200MHz
100MHz
LVCMOS
3.3V Or
DDR 3.3V
LVDS 2.5V
9 shift register chains with various configurations :
Input clock 200MHz / Input Data 100MHz (9 chains)
Some chains has different output level technologies
Inverter chain (X4) has been added on various paths
For chains no.8 and no.9, 200 MHz clock has been generated through PLLx10
This slide and next one describes the design 1, which is made of 9 sift register chains with various configurations.
An input clock 200MHz / Input Data 100MHz is applied to all chains. Some chains has different output technologies. Inverter chains has been added on various path. On the last chains, 200 MHz clock has been generated through PLL, time 10.
ESA / CNES March 2017

11. Single Event Upset and Functional Interrupt
Design 1 : Shift register chain 1
Filling at least 40% of the reconfigurable blocks 2
Chain
Clock
Logic
Logic to
I/O type
Between
Enable pins
CLR pins
registers 1
200 Mhz no
LVCMOS 3.3V 2
yes 3 4 5
LVDS 2.5V 6
DDR 3.3V 7 8
20MHz x PLLx10 9 3 4
5&6 7
This slide is a recap of each chain configuration. The number of shift registers depends on the junction temperature and consumption.
8&9
ESA / CNES March 2017

12. Single Event Upset and Functional Interrupt
Design 1 : Shift register analysis
The Virtex4 board was generated for each chain, a common external clock of 200 MHz + input square signal of 100MHz.
The output of each shift register chain was checked by the Virtex4 board
When an error is detected, an SEU is counted
When there is more than one consecutive error, a long SEU is counted
If 50 consecutives SEU are observed, a SEFI is counted
Lire in fo slide
The schematic below represents the signals applied on the parts. On the output curve, here on the right, we can see a detected SEU.
input
100MHz
Output
Clock
200MHz
Registers
Detected SEU
ESA / CNES March 2017

13. Single Event Upset and Functional Interrupt
Design 1 : Shift register results
SEE detected on shift registers application:
Mainly SEFI was detected.
SEUs and long SEUs was observed mainly on chain no. 8.
Events occured at same time on chains no. 8 and no. 9. These common events may be due to disruption in PLLx10.
During irraditions, the most observed effects were SEFI. SEUs and long SEUs was observed mainly on chain no. 8.
ESA / CNES March 2017

14. Single Event Upset and Functional Interrupt
Design 1 : Shift register Results
You can see here a cross section curve for long SEUs. The same sensity has been obseerved for SEUs.
ESA / CNES March 2017

15. Single Event Upset and Functional Interrupt
Design 1 : Shift register Results
The SEFI sensitivity is a bit higher than the SEUs and long SEUs sensitivity
The SEFI cross-section curve is shown here. As you can see, it is a bit higher than the SEUs curve.
ESA / CNES March 2017

16. Single Event Upset and Functional Interrupt
Design 2 : Block memory (BRAM)
36 Kbits Block RAM – 4096 address bits and 9 data bits
All memory will be written with two patterns 0xAA for odd address and 0x55 for even address (checkerboard pattern)
Various read/write cycles has been performed in order to classify errors into 3 types
Event classification:
Transient (error type 1)
Upset (error type 2)
Stuck bit (error type 3)
1 memory bock instantiated and initialized with checkerboard pattern.
Various read/write cycles has been performed in order to classify errors into 3 types, as you can see in this table.
ESA / CNES March 2017

17. Single Event Upset and Functional Interrupt
Design 2 : Block memory / Results
SEE detected on BRAM:
No MBUs was detected
No Type 1 SEU was detected
SEUs was detected of Type 2 and 3 (Stuck Bit), mainly Type 2
Few SEFI was detected
No MBU and no type 1 SEU has been detected.
We have mainly observed type 2 SEUs and few type 3 SEUs.
For this design, we have also detected a few SEFIs in contrast with the first design.
A reprogramming DUT process was performed to resume the test after SEFI.
ESA / CNES March 2017

18. Single Event Upset and Functional Interrupt
Design 2 : Block memory / Results
A strong SEU sensitivity up to a LET of 1.83MeV, in spite of only one BRAM was used
We can observe a strong SEU sensitivity up to a LET of 2 MeV, in spite of only one BRAM was used. Therefore, only a little area of the die is represented.
ESA / CNES March 2017

19. Single Event Upset and Functional Interrupt
Design 3 : 32-bit counters (ESA design) 32 32 32 32
All the n « 32-bit counters » were initialized with different values
At one point, values from counters were captured by the registers
The snapshot controller allows to recover the data from the counters, then send it to one register output at a time
The last design consist of n time 32bit counters and each counter value is sent to output one by one.
ESA / CNES March 2017

20. Single Event Upset and Functional Interrupt
Design 3 : 32-bit counters (ESA design)
The Virtex4 board was comparing the 32-bit data output with internal counter every two clock cycles
If 1 bit in the output word is wrong then 1 SEU is counted
If several bits in the output word are wrong then 1 MBU is counted
If 50 consecutive SEUs or MBUs are observed then 1 SEFI is counted
A reference counter has been implemented in Viretx4 board so the Virtex4 board can compare the output value of the DUT with the reference counter run at 200MHz.
When the counter output value is different than the reference counter value, an SEU or MBU is counted.
For each error, a frame consist of the wrong value and of the expected value is sent to the host software.
If there are more than 50 consecutive errors, an SEFI is counted and a reprogramming is performed to the FPGA.
ESA / CNES March 2017

21. Single Event Upset and Functional Interrupt
Design 3 : 32-bit counters (ESA design)
SEE detected on 32-bit Counter:
High amount SEFIs was detected up to LET of 1.83MeV.cm²/mg
Few SEUs and MBUs was detected
Few SEUs and MBUs has been observed. On the other hand, we have observed a high amount of SEFI up a LET of 2 MeV around.
ESA / CNES March 2017

22. Conclusion SEE characterisation
Part is not sensitive to SEL, but there were no destructive increase current during the irradiation
SEFI sensitivity depends of FPGA usage capacity, thus of memory configuration (CRAM) number used
A FPGA reprogramming process was performed after every SEFI
Proton campaign should be considered
To conclude
No SEL was observed, an increase current occurs under irradiation, but the part were not dammaged.
The SEFI sensitivity depends of CRAM number usage; and to resume the test, a reprogramming process of FPGA must be performed.
A proton campaign should be considered to determine the SEFI sensitivity under proton beam.
ESA / CNES March 2017

23. Thank you for your attention
Any question ?
ESA / CNES March 2017

24. Shift Registers Results
We have observed few event in the internal PLL, but up to a LET of 1.83MeV
ESA / CNES March 2017

25. BRAM Results ESA / CNES March 2017
few event of type 3 has been detected up to a LET of 10MeV
ESA / CNES March 2017

26. BRAM Results ESA / CNES March 2017
Very few event of type 3 has been detected up to a LET of 18MeV
ESA / CNES March 2017