1. A Comparison of Field Programmable Gate
Arrays and Digital Signal Processors in
Acoustic Array Processing
Thesis Presentation by
Jeremy Stevenson

2. Overview Introduction Algorithm used to test Hardware used
Software used
DSP implementation
FGPA implementation
Conclusions

3. Introduction Comparison of FPGAs to DSPs
Field Programmable Gate Arrays
Digital Signal Processors
Performance, Coding, and Utility of tools were focused upon
Sound Localization was the test application

4. Diagram of Test System

5. Algorithm Simulate A/D conversion and peak detect Remove any DC offset
1000 sample buffer
When a threshold is met, 500 more samples are taken
Remove any DC offset
Find the average value of the signal
Subtract that value from all samples

6. Effect of Offset Removal

7. Correlation Shortened range Shifting is done about the peak
Does not correlate full signal
500 samples before and after the peak are used
Shifting is done about the peak
20 shifts behind the peak by shifting the right channel
20 shifts before the peak by shifting the left channel

8. Comparison of Correlation Methods

9. Algorithm Cont. The maximum of each correlation is found
A time delay is found using the maximums
A right triangle is formed using the distance between the microphone and the delay found earlier
An arctangent is used to calculate the angle

10. Equations
Calculation for the distance a sound wave traveled based on the sample delay
Calculation for the third leg of the triangle
Calculation of the angle of approach

11. Sound Acquisition Hardware
Yamaha MG10/2
4 XLR microphone inputs
Requires a separate sound card to sample
Nady SCM1000 microphones
Cardiod, figure eight, and omnidirectional condenser microphone

12. Sound Acquisition Hardware
Presonus Firepod
8 XLR microphone inputs
24-bit, 96 kHz sampling
Audio-technica MT830R microphones
Omnidirectional condenser microphone
30 to Hz response range

13. DSP Hardware Texas Instruments TMS320C6711 DSK
32-bit processor, up to 8 instruction/cycle
100 MHz clock rate
Communications via parallel port
16 MB memory for data storage

14. FPGA Hardware Nallatech XtremeDSP Virtex-II chip
3 million gates
96 18x18 multipliers
96 RAM modules
Commincates with computer over the PCI bus

15. System Modeling Software
Matlab 7 R14
Simple to code, compiles not needed
Used to generate a script, list of actions, that modeled a signal’s flow through the system
Simulink 6 R14
A visual modeling application
Used with System Generator to link Verilog to Matlab

16. DSP Software Code Composer Studio C coding Built in debugging tools
Profiling tool

17. FPGA Software Xilinx ISE System Generator for Simulink Verilog or VHDL
Timing and chip utilization reports
System Generator for Simulink
Blocks of VHDL/Verilog code
Fixed point support
Import data from Matlab

18. DSP Implementation Data loaded using a “probe point”
Feature that allows external data to be written to memory
A null function is used to mark a probe point
Data is read into memory
The type of data and number of entries are included in a header of the data file
One memory write at a time
Code operation halted until the end of file

19. DSP cont. Floating point numbers used
Algorithm was broken up into smaller functions
Offset removal in smoothing function
Correlation in correlate function
Some parallelism was used
Auto, x leads y and x lags y correlations
Angle determination in findangle function

20. FPGA Implementation

21. FPGA cont. Most of design was done using System Generator in Simulink
Libraries of common functions like multipliers and accumulators were used
16-bit fixed point numbers were used
15 decimal places
Numbers ranging from -1 to
CORDIC IP cores were used for the square root and arctangent

22. FGPA cont. Correlation was coding using ISE
Easier to implement control logic
Fixed point arithmetic had to be coded as well, not natively supported
Code imported to System Generator using a “black box” model
Allows Simulink to simulate unknown code by invoking ModelSim, a FGPA simulation tool

23. FPGA cont. Design wrapped up into a single block
Design passed tests such as synthesizing and fitting to a chip
Block allowed the design to be cosimulated, placed onto the chip to be part of the simulation

24. Test Files File name Type of Sound Distance Angle clap.wav handclap
110°
clap1.wav
70°
clap2.wav
75°

25. DSP Results Results when 3 test files were analyzed:
109.46°, 72.36°, 77.75°
Clock Cycles per section of code:
Code Size
Inclusive Cycles
Exclusive Cycles
main
288
527
smoothing
428
correlate
580
findangle
592
33668
23834

26. FPGA Results Results when 3 test files were analyzed:
111.32°, 72.66°, 77.03°
FPGA parts utilization:
Part
Number Used
Number Available
External IOB
110
484
MULT18X18 3 96
RAMB16 4
SLICE
3123
14336
BUFGMUX 2 16
TBUF
224
7168

27. Conclusions Performance Accuracy
FPGA calculations completed in ms
23005 clock cycles at 40 MHz
DSP calculations completed in ms
clock cycles at 100 MHz
Accuracy
All tests returned with error less than 5%

28. Conclusions Coding DSP FPGA Familiarity
Years of support to refine tools
Errors easily identified
2 weeks to develop
FPGA
Visual code building
Highly customizable blocks
3 months to develop

29. Conclusions Utilities DSP FPGA Recognized parallel portions of code
Watch window allowed variables to be monitored
FPGA
Logic trimming
ModelSim to view all signals in design at once

30. Future Work
Create a better interface between the soundcard and the FPGA/DSP
Test the system with higher sampling rates
Currently using 44.1 kHz and 96 kHz