1. Buttons and Debouncing Finite State Machine
Lab 6
Buttons and Debouncing
Finite State Machine

2. Lab Preview: Buttons and Debouncing
Mechanical switches “bounce”
vibrations cause them to go to 1 and 0 a number of times
called “chatter”
hundreds of times!
We want to do 2 things:
“Debounce”: Any ideas?
Synchronize with clock
i.e., only need to look at it at the next +ve edge of clock
Think about (for Lab):
What does it mean to “press the button”? Think carefully!!
What if button is held down for a long time?

3. Verilog design patterns for sequential logic

4. wire vs. logic a signal of type wire must be continuously assigned
since it cannot have memory
wire z;
assign z = a&b | c&d; // combinational func
wire zz = a&b | c&d; // shorter form

5. wire vs. logic logic can be intermittently updated
holds its value between updates
must specify the discrete events when updates occur
Example 1: counter
logic [3:0] z = 0;
clock)
z <= z + 1; // sequential func
Example 2: stimulus in tester
logic [31:0] A = 0;
initial begin
#10 A = 1; // discrete time instants
#10 A = 2; …
end

6. wire vs. logic As a special case: “intermittent” includes “continuous”
logic can also be assigned
logic zz;
assign zz = a&b | c&d; // zz becomes a wire
update instants are implicitly defined
whenever a or b or c or d changes value  update zz
since updates occur whenever inputs change, SystemVerilog infers a combinational circuit
with no need for latches/flipflops

7. Always Block
Example
( sensitivity list )
statement;
Sensitivity list determines when statements are evaluated
Could think of it as “statement is evaluated whenever one of values in sensitivity list changes”

8. Blocking vs. Non-blocking Assignment
Blocking assignments:
Equal sign indicates blocking statements
occur in text order
B = A;
C = B;
Result: new contents of B are in C, so all have contents of A
Non-blocking assignments:
RHS of all <= lines within a begin-end block are evaluated in parallel, then assigned to LHS signals in parallel
B <= A;
C <= B;
Result: new B is the value of A, but new C is the old B!

9. This is Not Software!
Don’t assign to same signal in more than one always_ff block
The always_ff blocks are concurrent
Doesn’t make sense to set a flipflop from two different inputs
For sequential logic: Use only non-blocking assignments
you usually don’t mean one-by-one execution anyway
yields the design pattern that is recognized by the compiler
each logic on the LHS becomes a flip-flop/register
each RHS becomes the input D to the flipflop
sensitivity list (posedge clock) determines the clock signal
enables/resets are also inferred if described
But for testers: Blocking assignments are more convenient!

10. SystemVerilog Syntax: Initialization
Can initialize flipflops/registers at declaration
logic onebit = 1’b 0;
logic [3:0] fourbits = 4’b 1011;
logic [23:0] cnt = 0; // widths default to 32 bits
// and are padded
// or truncated (keep LSBs)
DO NOT initialize combinational logic!
initial values of a combinational circuit are determined solely by the initial values of its inputs
logic z = 1’b 0; // should NOT initialize!
assign z = x & y; // a combinational func

11. SystemVerilog Syntax: Initialization
Do not confuse initialization with shorter form of assignment
wire A = B | C; // short form
is equivalent to:
wire A; // type declaration AND
assign A = B | C; // continuous assignment
But…
logic A = B | C; // is initialization ONLY
update behavior still needs to be described, e.g.:
clock)
A <= D^E;

12. Finite State Machines (FSMs)

13. Finite State Machines “FSMs”
How to design machines that go through a sequence of events
“sequential machines”
Basically: Close the feedback loop in this picture:

14. Synchronous Sequential Logic
Flip-flops/registers contain the system’s state
state changes only at clock edge
so system is synchronized to the clock
all flip-flops receive the same clock signal (important!)
every cyclic path must contain a flip-flop

15. Finite State Machine (FSM)
Consists of:
State register that
holds the current state
updates it to the “next state” at clock edge
Combinational logic (CL) that
computes the next state
using current state and inputs
computes the outputs
using current state (and maybe inputs)

16. More and Mealy FSMs
Two types of finite state machines differ in the output logic:
Moore FSM:
outputs depend only on the current state
Mealy FSM:
outputs depend on the current state and the inputs
can convert from one form to the other
Mealy is more general, more expressive
In Both:
Next state is determined by current state and inputs

17. Moore and Mealy FSMs

18. Verilog coding: procedural style

19. Verilog procedural statements
All variables/signals assigned in an always statement must be declared as logic
Why?
Because always allows intermittent updates to a signal
So, the signal could turn out to be combinational or sequential…
… depending on the actual description

20. Verilog procedural statements
These statements are often convenient:
if / else
case, casez
more convenient than “? : ” conditional expressions
especially when deeply nested
But: these must be used only inside always blocks
some genius decided that!
Result:
designers often want to use if-else/case for describing combinational logic for convenience/readability
… instead of being limited to just “? : ” expressions
so SystemVerilog introduced a new construct: always_comb
the compiler will try to check to see that the description is indeed a combinational function

21. Example: Comb. Logic using case
module decto7seg(input wire [3:0] data,
output logic [7:0] segments); // no flipflops actually
always_comb // used -> combinational
case (data)
0: segments <= 8’b ;
1: segments <= 8’b ;
2: segments <= 8’b ;
3: segments <= 8’b ;
4: segments <= 8’b ;
5: segments <= 8’b ;
6: segments <= 8’b ;
7: segments <= 8’b ;
8: segments <= 8’b ;
9: segments <= 8’b ;
default: segments <= 8’b ; // required!!
endcase
endmodule
Note the “comb”:
it means that the compiler will check to make sure that the output is combinational.

22. Example: Comb. Logic using case
module decto7seg(input wire [3:0] data,
output logic [7:0] segments); // no flipflops actually
always_comb // used -> combinational
case (data)
0: segments <= 8’b ;
1: segments <= 8’b ;
2: segments <= 8’b ;
3: segments <= 8’b ;
4: segments <= 8’b ;
5: segments <= 8’b ;
6: segments <= 8’b ;
7: segments <= 8’b ;
8: segments <= 8’b ;
9: segments <= 8’b ;
default: segments <= 8’b ; // required!!
endcase
endmodule
Suppose we forget to include the default case. What have we described then?
An incomplete case statement would imply that segments should hold its value if no cases match!

23. Beware the unintended latch!
Very easy to unintentionally specify a latch/register in Verilog!
how does it arise?
you forgot to define output for some input combination
in order for a case statement to imply combinational logic, all possible input combinations must be described
one of the most common mistakes!
one of the biggest sources of headache!
you will do it a gazillion times
this is yet another result of the hangover of software programming
forgetting everything in hardware is parallel, and time is continuous

24. Cheat Sheet for comb. vs seq. logic
Sequential logic:
Use clk)
Use nonblocking assignments (<=)
Do not make assignments to the same signal in more than one always_ff block!
e.g.:
clk)
q <= d; // nonblocking

25. Cheat Sheet for comb. vs seq. logic
Combinational logic:
Use continuous assignments (assign …) whenever readable
assign y = a & b; OR
Use always_comb
All variables must be assigned in every situation!
must have a default case in case statement
must have a closing else in an if statement
do not make assignments to the same signal in more than one always_comb or assign statement

26. FSM Example: Sequence recognizer

27. A Sequence Recognizer Circuit has input, X, and output, Z
Recognizes sequence 1101 on X
Specifically:
if X has been 110 and next bit is 1, make Z high

28. How to Design States States remember past history
Clearly must remember we have seen 110 when next 1 comes along
Tell me one necessary state for this example…?

29. Beginning State Start state: let’s call it A
if 1 appears on input, move to next state B
output remains at 0
Input / Output

30. Second 1
New state, C
To reach C, must have seen 11

31. Next a 0 If 110 has been received, go to D
Next 1 will generate a 1 on output Z

32. What else? What happens to arrow on right?
Must go to some state. Where?

33. What Sequence? Here we have to interpret the problem statement
We have just seen 01
Is this beginning of new 1101?
Or do we need to start over w/ another 1?
Let us say that it is the beginning of a new run…

34. Cover every possibility
Must cover every possibility out of every state
For every state: X = 0 or 1
You fill in all the cases

35. Fill in

36. Full Answer

37. Verilog coding styles for FSMs

38. Sequence recognizer
Let us describe this as a Mealy FSM in SystemVerilog

39. Let’s encode states using enum
State encoding: convert symbolic state names to binary values
e.g., states = A, B, C, D
A=00, B=01, C=10, D=11
SystemVerilog provides enum construct
similar to C/Java
set of predefined constants
aids readability (and type/range checking in Java)
enum { A = 2’b 00, B = 2’b 01, C = 2’b 10, D = 2’b 11 } state, next_state;
also possible to leave encoding to compiler
enum { A, B, C, D } state, next_state;

40. FSM in SystemVerilog Step 1: State encoding module seq_rec (
input wire CLK, RESET, X,
output logic Z);
enum { A, B, C, D } state, next_state;
// Leaving encoding to compiler

41. Step 2: Next State logic Next State logic should be combinational
always_comb
case (state)
A: if (X == 1) next_state <= B;
else next_state <= A;
B: if(X) next_state <= C; else next_state <= A;
C: if(X) next_state <= C; else next_state <= D;
D: if(X) next_state <= B; else next_state <= A;
default: next_state <= A;
endcase
The last 3 cases do same thing.
Just sparse syntax.

42. Step 3: State Register Register with reset synchronous reset (Lab 3)
reset occurs only at clock transition
usually prefer synchronous reset
CLK)
if (RESET == 1) state <= A;
else state <= next_state; OR
state <= RESET ? A : next_state;
asynchronous reset
reset occurs whenever RESET goes high
CLK, posedge RESET)
use asynchronous reset only if you really need it!

43. Step 4: Output logic Output logic must be combinational always_comb
case(state)
A: Z <= 0;
B: Z <= 0;
C: Z <= 0;
D: Z <= X ? 1 : 0; // OR: Z <= X
default: Z <= 0;
endcase

44. Most common template for Mealy FSM
Use 3 always blocks
2 combinational logic
one for next state
one for outputs
1 state register
 easy to see everything clearly!

45. Final FSM in SystemVerilog
module seq_rec (
input wire CLK, RESET, X,
output logic Z);
enum { A, B, C, D } state, next_state;
always_comb // Process 1
case (state)
A: if (X == 1) next_state <= B;
else next_state <= A;
B: if(X) next_state <= C; else next_state <= A;
C: if(X) next_state <= C; else next_state <= D;
D: if(X) next_state <= B; else next_state <= A;
default: next_state <= A;
endcase
CLK) // Process 2
if (RESET == 1) state <= A;
else state <= next_state;
always_comb // Process 3
case(state)
A: Z <= 0;
B: Z <= 0;
C: Z <= 0;
D: Z <= X ? 1 : 0;
default: Z <= 0;
endcase

46. Comment on Code Could shorten it somewhat Template helps synthesizer
Don’t need three always_ clauses
Although it’s clearer to have combinational code be separate
Don’t need next_state, for example
Can just combine next_state logic with state update
Template helps synthesizer
Check to see whether your state machines were recognized by compiler (see output log)

47. Verilog: specifying FSM using 2 blocks
Let us divide FSM into two modules
one stores and update state
another produces outputs

48. FSM using two always blocks
module seq_rec (
input wire CLK, RESET, X,
output logic Z);
enum { A, B, C, D } state, next_state;
CLK) // Process 1
begin
if (RESET == 1) state <= A;
else case (state)
A: if (X == 1) state <= B;
else state <= A; // loops can be skipped
B: if(X) state <= C; else state <= A;
C: if(X) state <= C; else state <= D;
D: if(X) state <= B; else state <= A;
default: state <= A;
endcase // default not required
// for sequential logic!
end
always_comb // Process 2
case(state)
A: Z <= 0;
B: Z <= 0;
C: Z <= 0;
D: Z <= X ? 1 : 0;
default: Z <= 0;
endcase

49. Incorrect: Putting all in one always
Using one always block
generally incorrect! (But may work for Moore FSMs)
ends up with unintended registers for outputs!
AVOID!
CLK) // a single process for entire FSM
case (state)
A: if(X) begin state <= B; Z <= 0; end;
B: if(…) begin state <= C; Z <= 1; end;
C: if(…) begin state <= …; Z <= …; end;
D: if(…) begin state <= …; Z <= …; end;
endcase

50. My Preference The one with 3 always blocks Follow my template
Easy to visualize the state transitions
For really simple state machines:
2 always blocks is okay too
Never put everything into 1 always block!
Follow my template
lab6_fsm_template.sv (posted on the website)