1. Guerilla Section #4 10/05 SDS & MIPS Datapath
Computers are Cool!!!

2. FSMs
An abstract machine which can be in one of one of a finite number of states before receiving input and transitioning to another.
We start at a state and given an input, we follow some edge to another (or the same) state. Possibly outputs as well.
With combinational logic and registers, any FSM can be implemented in hardware.
Finite number of states
Input leads you from one state to another (or back to the same state)

3. FSM example
This FSM takes inputs of 0 or 1, and outputs 1 after seeing a group of three consecutive 1’s, and 0 otherwise.

4. What is a Synchronous System?
All operations coordinated by a central clock
Consist of two basic types of circuits, combinational logic and sequential logic
Combinational Logic (CL) circuits perform a function on its inputs, e.g. add them and output the result.
ALUs
Sequential Logic (SL) circuits store information, input and output are updated on flip flop of central clock. Used to synchronize flow of information between CL circuits.
registers

5. Review of timing terms
Setup Time: when the input must be stable before the edge of the CLK
Hold Time: when the input must be stable after the edge of the CLK
“CLK-to-Q” Delay: how long it takes the output to change, measured from the edge of the CLK
Camera Analogy Timing:
Set up time: don’t move since about to take picture
Hold time: need to hold still after shutter opens until camera shutter closes
Time to click data: time from open shutter until can see image on output (viewscreen)

6. Critical Path
The critical path is the path data could flow through in a circuit which would cause the longest delay.
Max delay = Setup Time + CLK-to-Q Delay + CL Delay
Assuming we have no registers, and all CL gates have a delay of 10 ns, what’s the critical path and max delay of the circuit below?

7. Critical Path
The critical path is the path data could flow through in a circuit which would cause the longest delay.
Max delay = Setup Time + CLK-to-Q Delay + CL Delay
Assuming we have no registers, and all CL gates have a delay of 10 ns, what’s the critical path and max delay of the circuit below?
40 ns

8. Max Clock Frequency
When there are registers in the circuit, there are constraints on clock frequency
Min Period = Max Delay
Max Freq = 1/Min Period
Max clock frequency limited by time needed to get correct next state to register (t_setup)
Two constraints on max clock frequency
t_hold <= t_input <= t_clk_period - t_setup

9. Max frequency/Hold time example
Each logic gate has a combinational logic delay of 10ns, the clk-to-q delay is 5ns and the setup time is 15ns.
Calculate the minimum clock period that will allow the circuit to function correctly.

10. Max frequency/Hold time example
Each logic gate has a combinational logic delay of 10ns, the clk-to-q delay is 5ns and the setup time is 15ns.
Calculate the minimum clock period that will allow the circuit to function correctly.
5ns + 3 * 10ns + 15ns = 50ns
I need time to wait for the input to update on the register
+ I need time to calculate/do ALL of my logic (LONGEST PATH)
+ I need time to set up the result in the register
= 50ns

11. Max frequency/Hold time example
Each logic gate has a combinational logic delay of 10ns, the clk-to-q delay is 5ns and the setup time is 15ns.
2) Assuming the hold time of the registers is 20ns, calculate the minimum combinational logic delay per logic gate for the circuit to function correctly.

12. Max frequency/Hold time example
Each logic gate has a combinational logic delay of 10ns, the clk-to-q delay is 5ns and the setup time is 15ns.
2) Assuming the hold time of the registers is 20ns, calculate the minimum combinational logic delay per logic gate for the circuit to function correctly.
5ns + 3 * 10ns + 15ns = 50ns
I need time to wait for the input to update on the register
+ I need time to calculate/do ALL of my logic (LONGEST PATH)
+ I need time to set up the result in the register
= 50ns

13. Note about Pipelining
Inserting SL units (registers) between CL Units decreases the length of the critical path, thus allowing the maximum clock frequency to rise and improving data throughput.
However, more registers means greater latency between the first input and first output

17. add $t0 $t1 $t2 #what do i do??

18. 1. Hi. add $t0 $t1 $t2 #WHO AM I???? 3. OH I DO ADDING
2. Oh I am R-type! t0=rd
t1=rs
t2=rt
4. Nah man.

19. add $t0 $t1 $t2
1. Hi.
Increment PC by the appropriate ammount → PC = PC + 4 or new address

20. 2. Oh I am R type and t0=rd, t1=rs, t2=rt add $t0 $t1 $t2
Decodes: register numbers, opcode, funct (if needed), shamt, immedate, or address (depends on instr)
Does all of this, but only necessary fields used later on

21. 3. I DO ADDING
add $t0 $t1 $t2

22. 4. Nah.
add $t0 $t1 $t2

23. 5. t0 needs that info
add $t0 $t1 $t2

24. WHICH INSTRUCTION IS THE ONLY ONE THAT USES ALL 5 STAGES?

25. You have these Controls that tell your Datapath what to do!!

26. regWr = am I going to write to a register?
RegDst = should I write the result to $rd or $rs?
nPC_sel = do I get normal PC + 4 or PC + some branch/jump?
ALUSrc = $rs is always the first argument, but should the second argument be $rt or an immediate?
ExtOp = sign or zero extend the immediate?
ALUCtr/Alu = what operation do I do in the ALU? Add, subtract, multiply?
MemWr = am I writing to memory?
MemToReg = if I got a value from memory do I need to go back to the regfile and store the memory value in a register?

27. regWr = am I going to write to a register?
RegDst = should I write the result to $rd or $rs?
nPC_sel = do I get normal PC + 4 or PC + some branch/jump?
ALUSrc = $rs is always the first argument, but should the second argument be $rt or an immediate?
ExtOp = sign or zero extend the immediate?
ALUCtr/Alu = what operation do I do in the ALU? Add, subtract, multiply?
MemWr = am I writing to memory?
MemToReg = if I got a value from memory do I need to go back to the regfile and store the memory value in a register?