1. Elec 2607 Digital Switching Circuits
Lecture 7 & 8: Digital Logic
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3. ANOTHER FORM OF Digital Logic
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4. 2017
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5. Lots to do in two lectures
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6. The most basic digital latch
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7. The most basic digital latch
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8. The most basic digital latch
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10. Basic latch with SET and RESET
O10
101
Same = stable
Same = stable
Basic latch with SET and RESET
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11. Basic latch with SET and RESET
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12. Basic latch with SET and RESET
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14. Asserted = DOES ITS JOB WHEN ….
Basic latch with SET and RESET
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15. Asserted = DOES ITS JOB WHEN ….
Stable 0
Asserted = DOES ITS JOB WHEN ….
Change 0  1
Stable 1
Basic latch with SET and RESET
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16. Asserted = DOES ITS JOB WHEN ….
Basic latch with SET and RESET
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17. Asserted = DOES ITS JOB WHEN ….
Basic latch with SET and RESET
Stable 1
Change 1  0
Stable 0
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18. 6
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19. The RESET-SET (RS) Latch
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20. S = SET R = RESET Additional notes on Board The RESET-SET (RS) Latch
Start with Q = 0, R = 1, S = 0
Change S to 1: Q goes to 1 and stays at 1
Change S to 0: Q stays a 1
Latch is SET using S asserted high
Start with Q = 1, R = 1, S = 0
Change R to 0: Q goes to 0 and stays at 0
Change R to 1: Q stays at 0
Latch is RESET using R asserted low
The RESET-SET (RS) Latch
S = SET
R = RESET
Additional notes on Board
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ELEC 2607 Lecture 7 & 8:

21. The RESET-SET (RS) Latch2
Complement of logic
Using invert on input
The RESET-SET (RS) Latch
Start with Q = 0, L = 1, S = 1
Change S to 0: Q goes to 1 and stays at 1
Change S to 1: Q stays a 1
Latch is SET using S asserted low
Start with Q = 1, L = 1, S = 1
Change L to 0: Q goes to 0 and stays at 0
Change L to 1: Q stays at 0
Latch is RESET using R asserted low
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ELEC 2607 Lecture 7 & 8:

22. S = SET R = RESET Additional notes on Board The RESET-SET (RS) Latch
Start with Q = 0, R = 1, S = 0
Change S to 1: Q goes to 1 and stays at 1
Change S to 0: Q stays a 1
Latch is SET using S asserted high
Start with Q = 1, R = 1, S = 0
Change R to 0: Q goes to 0 and stays at 0
Change R to 1: Q stays at 0
Latch is RESET using R asserted low
The RESET-SET (RS) Latch
S = SET
R = RESET
Additional notes on Board
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ELEC 2607 Lecture 7 & 8:

23. The RESET-SET (RS) Latch2
Complement of logic
Using invert on input
Start with Q = 0, R = 0, S = 0
Change S to 1: Q goes to 1 and stays at 1
Change S to 0: Q stays a 1
Latch is SET using S asserted high
Start with Q = 1, R = 0, S = 0
Change R to 1: Q goes to 0 and stays at 0
Change R to 0: Q stays at 0
Latch is RESET using R asserted high
The RESET-SET (RS) Latch
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24. 3
See Floyd page 377
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25. Note on feedback signals
OUTPUT Q
Q as input
Use “q”
lowercase
The TRANSPARENT (D) Latch
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26. The TRANSPARENT (D) Latch
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27. 2
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28. The TRANSPARENT (D) Latch
Transparent High
Transparent Low
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29. The TRANSPARENT (D) Latch
Transparent High
Transparent Low
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30. The TRANSPARENT (D) Latch
Transparent High
Transparent Low
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32. The Edge triggered (D) Flip Flop
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33. The Edge triggered (D) Flip Flop
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34. The Edge triggered (D) Flip Flop
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35. 2
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38. Master-Slave Edge Triggered Flip Flop
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39. Master-Slave Edge Triggered Flip Flop
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Timing diagram follows next

40. This device acts as a falling edge triggered flip-flop: The output is changed at the falling edge of the clock cycle.
clock
Falling edge triggered
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41. Master-Slave Edge Triggered Flip Flop
Change occurs at falling edge
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42. 2 T
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43. Propagation delay taken as zero
H H
T T
T T
H H
T T
H H
T T
H H
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Propagation delay taken as zero

44. Propagation delay taken as zero
H T
T H
T H
H T
T H
H T
T H
H T T H T H T H T H H T H T H T H T
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Propagation delay taken as zero

45. Propagation delay taken as zero
T T
T T
T T
T T
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Propagation delay taken as zero

46. Propagation delay taken as zero
T H
H T
T H
H T
T H
H T
T H
H T
Propagation delay taken as zero
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47. Special Controls: Asynchronous Reset
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49. Special Controls: Synchronous Reset
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51. Flip-flop circuits: Divide Clock Frequency by 2
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53. Flip-flop circuits: Shift register
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55. Flip-flop Memory Values = STATES
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57. Special Controls: Enable
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59. SUMMARY
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60. 16/11/2018
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