1. ALCT, TMB Status, Peripheral Crate Layout, CSC Event Display
Jay Hauser
University of California Los Angeles
ALCT
TMB
Periph Crate
Event Display

2. FPGA Mezzanine Boards for ALCT, TMB, MPC, etc
516 boards produced
204 boards assembled
105 XCV1000 for ALCT672 (also TMB, MPC)
99 XCV600 for ALCT384
7 sent to Rice for MPC and evil purposes
Found a bad batch of Eproms, working with Xilinx to understand problem
Next assembly order of 230 boards – parts will be shipped next Monday
Just ordered last baseline batch of FPGAs – 80 XCV600s for ME1/1

3. ALCT384 Boards 89 boards have been assembled
161 boards to be delivered in next 3 weeks
About 50 boards shipped to FAST sites
Testing:
2 test setups working, 4 students
Testing can go faster than anticipated – net through-put of 3/day possible, including burn-in
1 hole in testing procedure found by FAST sites (short between threshold wires), fixed

4. ALCT-672 and ALCT–288 (ME4/1 boards not ok’ed for assembly, no FPGAs)
Assembly of 6 boards of each type is complete
3 ALCT-672 will be shipped to PNPI in next shipment from FNAL
On-chamber testing still not done  due to FAST site situation
Proceeding with production of 130 ALCT672 boards (allows ME4/1)
Still want to have on-chamber test before assembly
(ME4/1 boards not ok’ed for assembly, no FPGAs)

5. TMB Status 18 boards assembled
Overcame severe assembly problems with connectors, etc.
14 boards debugged and working (full set of bench tests)
1 at UF and 1 at UC FAST site, 1 at OSU
2 at Rice = spares for U.S. FAST sites
Future: send 2 each to PNPI, IHEP, Dubna, 3 to CERN
Would like additional 1 at OSU, 2 at UCLA labs (grand total needs 16)
Integrated with ALCT and DMB at UCLA FAST site in April-May
VME library finished and released July 9
MPC output/return FIFOs debugged July-Aug
Next step for JK: build a TMB clock prototype board to investigate PHOS4 replacement options
Upcoming Oct tests with OSU and 2 chambers at UCLA

6. Current TMB Modes Centralized trigger handling added: Source Delay Ext
Type
Source
Delay
Ext
Description
CLCT VPF No N
Cathode LCT Pattern Trigger, this is the normal trigger mode (VPF=Valid Pattern Flag) 1
ALCT VPF
Adj Y
ALCT Trigger acting as Scintillator 2
ADB Test Pulse
Anode Test Pulse Trigger 3
DMB Ext Trig
DMB Calibration Trigger 4
CLCT Ext Trig
FAST Site Scintillator Trigger 5
ALCT Ext Trig
ALCT External trigger, force TMB readout if ALCT VPF absent 6
VME Ext Trig
VME External trigger, for self-test

7. TMB Firmware Plans I Top priorities, mainly for FAST sites:
Design FMM signal handling - currently “topical”
Change the key layer from 3 to 4 for software reasons.
Add di-strip and multiple patterns.
Di-strip patterns greatly increase (x4 to x16) the flux of cosmic ray CLCTs at the FAST sites.
Multiple patterns are included in the ORCA simulation

8. TMB Firmware Plans II Fancy stuff: Additional possibilities:
Basic stuff for CMS operation:
Make timing diagrams for the multi-pattern CMS-type design.
Improve the timing to the level required for CMS latency.
Add DAQ multi-buffer handling capability.
Fancy stuff:
Add suppression of spurious output caused by radiation upsets by, for instance, a triple-voted detection of continuous unchanging trigger or DAQ output.
Add RPC coincidence logic.
Additional possibilities:
Add trigger mode of L1A*(no LCT). This would require a lot of work on RAM storage of information and may not be supported by OSU for CFEB readout.

9. Peripheral Crate Layout
CMS IN 2000/004 “orientation” note updated
ME1/1 information included
Chambers to slots:
Loveless scheme: cable in sequential chamber order
As per Matveev drawings (June 02): T M B D M B T M B D M B T M B D M B T M B D M B T M B D M B M P C C B T M B D M B T M B D M B T M B D M B T M B D M B 1 2 3 4 5 6 7 8 9

10. ME1 Peripheral Crates
No DMB/TMB pair for ME1/A – just last cable to corresponding ME1/1 board pair
Chambers 4-12 correspond to DMB/TMB 1-9 in crate:

11. Periph. Crate Cross-Sections
Full-size and reduced-size (TMB)
VME64x cards + front panel (TMB shown)
9U x 100 mm VME transition cards
405 mm
100 mm
~25 mm
Backplane region incl. connectors
ALCT 1
SCSI-50
ALCT 2 SCSI-50
RPC 1
34-pin ribbon connectors
366.7 mm J1 J2
J3A
J3B
CFEB1
CFEB2 SCSI-50
CFEB3
CFEB4 SCSI-50
CFEB5 SCSI-50
RPC 2
RPC 3
RPC 4
VME64x cards + front panel (TMB shown)
6U x 100 mm VME transition cards
280 mm
100 mm
~25 mm
Backplane region incl. connectors
366.7 mm J1 J2
J3A
J3B
CFEB1
SCSI-50
CFEB2 SCSI-50
CFEB3
CFEB4 SCSI-50
CFEB5 SCSI-50
RPC 4
RPC 3
RPC 1
RPC 2
34-pin ribbon connectors
ALCT 1
SCSI-50
ALCT 2 SCSI-50

12. Brian Mohr Event Display
Tabs for CFEB, Comparator, ALCT data displays
Reads FAST site data (raw format)
ROOT allows zooming, rotation
Will add projections
Dumps of Event, CFEB, TMB data for debugging