1. A 0.5V 30.78µW 78dB DR using 2nd order Sigma Delta Modulator for Biomedical Application
Presentation By
Syeda Nazia Fathima
Co-Authors
Mr. M.A. Raheem
Mr. K. Manjunathachari
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9th May 2018

2. Contents Abstract Area of Work Problem & Solution Target Specification
Operational Amplifier
Novel Architecture for 2nd Order Sigma Delta Modulator
Simulation results
Comparison table
Conclusion
References
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3. Abstract
To design a low pass 2nd order CT-DT sigma-delta modulator for medical implants. OSR of 50 and Bandwidth of 500Hz targeted at medical application
Design and Analysis of Operational Amplifier is the key building block for Analog IC design targeted at Wireless-Medical application.
Implemented in CMOS 0.18µm tech, 0.5 V supply, Gain is observed 62.7 dB & DR 78dB and Power consumption of 30.78μW
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4. Introduction Area of Analog and Mixed Signal VLSI Design.
Objective of the paper is to Design CT-DT Multi bit Sigma Delta modulator for Medical Applications.
The basic block diagram of Sigma Delta Modulator
SQNR is proportional to OSR and in broadband applications (bandwidth>5 MHz) a very high OSR is not possible.
The loss in SQNR due to lowering of OSR can be compensated by increasing the order of the filter or by using a higher bit Quantizer
Higher order filters – stability problem
Increase Quantization Levels
Hence use a multibit DAC in feedback path.
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5. Problem & Solution
Low power consumption is the most critical design requirement for medical implant devices.
For high-precision measurements in medical implants the ΔΣ modulators (ΔΣMs) are gaining interest.
Operational amplifiers are the most critical block of the ΔΣ modulators design, the combination of CT and DT 2nd Order Hybrid Modulator is designed.
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6. Motivation
J. Goes, Member, IEEE, N. Paulino, H. Pinto, R. Monteiro, Bruno Vaz, Member, IEEE, and A. S. Garção, “Low-Power Low-Voltage CMOS A/D Sigma-Delta Modulator for Bio-Potential Signals Driven by a Single-Phase Scheme,” IEEE Transactions on Circuits and Systems,: Regular Papers vol. 52, no. 12, pp , Dec
Voltages and frequency ranges of some common bio-potential signals (in gray color); dc potentials (in white color) include intracellular voltages as well as voltages measured from several points on the body; the black-color bars represent the required DR
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7. Target Specifications
Parameter
Value
Order
second order
Signal Bandwidth
500Hz
Sampling Frequency
50 KHz
OSR
50(fs/2b.w)
SNR
64dB- 77dB
Resolution
8 bits
Quantizer
1 bit quantizer (2 level)
Topology
CIFB (Cascade-
of-integrators, feedback form)
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8. Architecture & System Level Design
𝑌= 𝑥+ 𝑄 𝑅 𝑄 𝑅𝑆 𝑄 𝑛
A The noise Q2 is made by integrator R and Qn is formed by both integrators R and S. Hence the first integrator R is desperate for the overall noise drop. .
However the 2nd integrator S is lesser important, consequently its performance can be ascended down to decrease the power consumption along with its existing consumption. is removed.
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9. Novel Architecture & System Level Design
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10. Theoretical Analysis ISMS18 ID 1570441545 9th May 2018 L = 1µm
Step1: calculation of Cc value
To have a phase margin of 60º, the condition is
Cc ≥ 0.22 Cl
Cc ≥ 0.22 x 0.5pF
Cl = 1.1pF
Step2 : Calculation of bias current
Wk. SR =
I5 = (SR) (Cc)
I5 = (5V/us) (1.1pF) = 5.5pF
I5 ≈ 10µA
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11. Step3 : Sizes of M1 and M2 ISMS18 ID 1570441545 9th May 2018
So, we can say 𝑉 𝑖𝑛−𝑚𝑎𝑥 = ICMR(+)
𝑉 𝐷1 ≥ 𝑉 𝐷𝐷 − 𝑉 𝑠𝑔3
𝑉 𝐷1 = 𝑉 𝐷𝐷 −[ 2 𝐼 3 𝜇 𝑝 𝐶 𝑜𝑥 𝑤 𝐿 | 𝑉 𝑡𝑝3 |]
Thus, ICMR(+) = 𝑉 𝐷1( min ) + 𝑉 𝑡1(𝑚𝑖𝑛)
ICMR(+) = 𝑉 𝐷𝐷 −[ 2 𝐼 3 𝜇 𝑝 𝐶 𝑜𝑥 𝑤 𝐿 | 𝑉 𝑡𝑝3 |] + 𝑉 𝑡1(𝑚𝑖𝑛)
𝑤 𝐿 3,4 = 2𝐼 3 𝐾 𝑝 ( 𝑉 𝐷𝐷 −𝐼𝐶𝑀𝑅 + −| 𝑉 𝑡𝑝3(𝑚𝑎𝑥) |+ 𝑉 𝑡1(𝑚𝑖𝑛) ) 2
On substituting all the values in above equation, we get
𝑤 𝐿 3,4 ≈ 18.3
Step3 : Sizes of M1 and M2
Wk, unit gain frequency is given by
𝑊 𝑇 = 𝑔 𝑚 / 𝐶 𝑐 𝑔 𝑚1 = 2𝜋 𝑓 𝑇 𝐶 𝑐
Thus, 𝑔 𝑚1 = 5.5µ
Let 𝑔 𝑚1 = 10µΩ-1
Wk. 𝑤 𝐿 1,2 = 𝑔 𝑚1 ² 2 𝐼 𝐷 𝜇 𝑛 𝐶 𝑜𝑥
Where, 𝐼 𝐷 = 𝐼 5 2
𝑤 𝐿 1,2 = 8.5
Step4: sizes of M3 and M4
For M1 to be in saturation,
𝑉 𝐷1 ≥ 𝑉 𝑔1 − 𝑉 𝑡1
𝑉 𝑔1 ≤ 𝑣 𝐷1 + 𝑉 𝑡1
𝑉 𝑖𝑛 ≤ 𝑉 𝐷1 + 𝑉 𝑡1
𝑉 𝑖𝑛−𝑚𝑎𝑥 = 𝑉 𝐷1 + 𝑉 𝑡1
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12. Step 5: Size of M5
For M1 and M5 to be in saturation, when 𝑉 𝑖𝑛 is decreased, the condition is
𝑉 𝑖𝑛 ≥ 𝑉 𝑔𝑠1 + 𝑉 𝑑𝑠𝑎𝑡5
𝑉 𝑖𝑛−𝑚𝑎𝑥 = 𝑣 𝑔𝑠1 + 𝑉 𝑑𝑠𝑎𝑡5
𝑉 𝑖𝑛−𝑚𝑎𝑥 =𝐼𝐶𝑀𝑅(−)
𝐼𝐶𝑀𝑅 − = 𝑉 𝑔𝑠1 + 𝑉 𝑑𝑠𝑎𝑡5
ICMR(−) = 2 𝐼 1 𝜇 𝑛 𝐶 𝑜𝑥 𝑤 𝐿 𝑉 𝑡1( max ) + 𝑉 𝑑𝑠𝑎𝑡5
𝑉 𝑑𝑠𝑎𝑡5 = ICMR(−) − 2 𝐼 1 𝛽 𝑉 𝑡1( max )
From, 𝑉 𝑑𝑠𝑎𝑡5 we can obtain size of M5 using the relation,
𝑤 𝐿 5 = 2 𝐼 5 𝜇 𝑛 𝐶 𝑜𝑥 𝑉 𝑑𝑠𝑎𝑡5 2 ≈ 9
Step6 : Size of M6
To have a PM=60º, condition is that zero of the system should be much larger than the UGB.
Z ≥ 10* UGB
𝑔 𝑚6 / 𝐶 𝑐 =10 * 𝑔 𝑚1 / 𝐶 𝑐
𝑔 𝑚6 = 10 * 𝑔 𝑚1
If ideal mirroring occurs, then 𝑉 𝑔𝑠3 = 𝑉 𝑔𝑠4 = 𝑉 𝑔𝑠6
Thus, in the current equation only W/L will be variable.
𝑤 𝐿 𝑤 𝐿 4 = 𝐼 6 𝐼 𝑤 𝐿 𝑤 𝐿 4 = 𝑔 𝑚6 𝑔 𝑚4
Thus, we obtain the size of M6 as,
𝑤 𝐿 6 = 𝑔 𝑚6 𝑔 𝑚4 * 𝑤 𝐿 4 ≈ 20
Step7: Size of M7
The essential condition to ensure that there is no systematic offset voltage is,
𝑤 𝐿 𝑤 𝐿 4 = 2 𝑤 𝐿 𝑤 𝐿 𝑤 𝐿 7 = 2 𝑤 𝐿 𝑤 𝐿 * 𝑤 𝐿 4 ≈ 15
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13. (a) Load-Compensated OTA (b) Miller-Compensated OTA
𝐴 0 = 𝑔 𝑚1 𝑅 𝑜𝑢𝑡1 × 𝑔 𝑚5 𝑅 𝑜𝑢𝑡2
𝐺𝐵𝑊= 𝑔 𝑚1 2𝜋 𝐶 𝑀
𝐺𝐵𝑊= 𝑔 𝑚1 𝑔 𝑚5 𝑅 𝑜𝑢𝑡2 2𝜋 𝐶 𝐿
𝐼 𝐷1 =𝐺𝐵𝑊.𝜋. 𝑉 𝐺𝑆 − 𝑉 𝑡ℎ . 𝐶 𝑀
𝑔𝑚𝑖=𝑔𝑚= 2 𝐼 𝐷1 ( 𝑉 𝐺𝑆 − 𝑉 𝑡ℎ )
𝑔 𝑚4 2𝜋( 𝐶 𝑀 + 𝐶 𝐿 ) =3.𝐺𝐵𝑊
𝐺𝐵𝑊= 𝑔 𝑚 2 𝑅 𝑜𝑢𝑡1 2𝜋 𝐶 𝐿 = 𝑔 𝑚 2 2𝜋 𝐶 𝐿 ( 𝜆 𝑛 + 𝜆 𝑝 ) 𝐼 𝐷1
𝐼 𝐷4 =𝐺𝐵𝑊.𝜋. 𝑉 𝐺𝑆 − 𝑉 𝑡ℎ .(3 𝐶 𝑀 +3 𝐶 𝐿
𝐼 𝑀𝑖𝑙𝑙𝑒𝑟 =2× 𝐼 𝐷1 + 𝐼 𝐷4 =𝐺𝐵𝑊.𝜋. 𝑉 𝐺𝑆 − 𝑉 𝑡ℎ .(8 𝐶 𝑀 +8 𝐶 𝐿 )
𝐼 2𝑆−𝐿𝐶 =4× 𝐼 𝐷1 = 𝐺𝐵𝑊.𝜋. 𝑉 𝐺𝑆 − 𝑉 𝑡ℎ 𝜆 𝑛 + 𝜆 𝑝 .(2 𝐶 𝐿 )
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14. Simulation Results Gain 62.7db PM 102.0450 BW 5 Mhz CMRR 62.77dB
Closed Loop dB
PSRR dB
Transient Response of Amplifier Gain, Phase, CMRR, PSRR, Stability and Power dissipation
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15. Simulation Results . Modulator input and output waveforms
Overlap of Input and Output
Simulation Results
Amplitude (V) .
Time(s)
Modulator input and output waveforms
FFT plot of ΣΔ ADC with 1-bit quantizer DAC DR= 78 dB.
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16. Comparison Parameter This work [1] [2] [6] [14] Process (nm) 180
Vdd (v)
0.5
0.7
1.8
Fs(kHz) 50 20 25
SNR 74 84 82 72 80
SNDR 70 81 78 DR 85 76 75
Power
30.78 µW
7.5 36
300 23 mW
FoMw (pJ/
step)
1.20
0.011
0.09
0.35
2.24
FoMs (dB)
169.10
172
176.4
155
147
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17. Conclusion
Finally a comparison between SQNR and effective number of bits in both cases is done.
It is observed that the SNR (with Ideal DAC) = 78.6 dB, with ENOB of 11.2 bits .
The power consumption of ADC with ideal DAC and µW respectively.
FoMw (pJ/ step) 1.02 which is compared with other state of art.
FoMs (dB) is achieved.
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18. References
Y. Chae and G. Han, “Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator,” IEEE Solid-State Circuits, vol. 44, no. 2, pp. 458–472, 2009.
J. Goes, B. Vaz, R. Monteiro, and N. Paulino, “A 0.9V modulator with 80 dB SNDR and 83 dB DR using a single-phase technique,” in IEEE ISSCC Dig. Tech. Papers, 2006, pp. 74–75.
A 250 mV 7.5μW 61 dB SNDR SC ΔΣ Modulator Using Near-Threshold-Voltage-Biased Inverter Amplifiers in 130 nm CMOS.
J. Sauerbrey, T. Tille, D. Schmitt-Land siedel, and R. Thewes, “A 0.7-V MOSFET-only switched op-amp modulator in standard digital CMOS technology,” IEEE J. Solid-State Circuits, vol. 37, pp.1662–1669, Dec
1.4V 13μW 83dB DR CT-ΣΔ modulator with Dual-Slope quantizer and PWM DAC for biopotential signal acquisition.
Fazli Yeknami and A. Alvandpour, “A 0.5-V 250-nW 65-dB SNDR Passive ΔΣ Modulator for Medical Implant Devices,” in Proc. IEEE international Sym.Circuits and Systems, May 2013, pp
M.A. Raheem, K. Manjunathaachari and Arifuddin sohel. “A Design of 2nd Order DT Sigma Delta Modulator for Medical Implants,” in Proc. IEEE Prime Asia, Dec 2015, /15/$31.00 ©2015 IEEE
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19. A Second Order Hybrid Continuous-Discreet Time Sigma-Delta Modulator.
M.A. Raheem, K. Manjunathaachari “presented as paper presentation IEEE paper “A Logarithmic DWA based Discrete Time Multi bit Sigma Delta Modulator” IEEE sponsored conference INBUSH ERA ISBN: at Amity University Greater Noida Feb ”
M.A. Raheem, Mohammed Arifuddin Sohel and Maliha Naaz “Design of Discrete Time Notch Filter for Biomedical Applications”, in Conference Proc. IEEE Device of Integrated Circuits Device /DEVIC
Maizan Muhamad, Norhayati Soin and Harikrihnan Ramiah “Design of Low Power Low Noise Amplifier using Gm- boosted Technique”, in Indonesian Journal of Electrical Engineering and Computer Science ISSN: , DOI: /ijeecs. v9. i3. pp
J.C. Candy and G.C. Temes, “Oversampling methods for A/D and D/A conversion”, Oversampling Delta-Sigma Data Convertors: Theory, Design and Simulation, pp
S. Pesenti, “Hybrid Continuous-Discreet-time Multi-bit Delta Sigma A/D Convertors with Auto-Ranging Algorithm”, PhD. Thesis no. 3912, 2008.
A Second Order Hybrid Continuous-Discreet Time Sigma-Delta Modulator.
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20. Thank You
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21. Acknowledgment
Dr. Mohammed Arifuddin Sohel, Head ECE Analog VLSI Group
Dr. Kaleem Fatima, Professor, ECE Dept, MJCET.
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