1. How to Create Area Constraints with PlanAhead
Xilinx Training

2. Objectives After completing this module, you will be able to:
Add Pblocks to your design with the Hierarchy viewer, Schematic viewer, and the Timing Report generator

3. Pblocks Pblocks are used to group logic
Assignment of a Pblock to a range of locations on the die makes it an area constraint
When starting to floorplan, the intent is to minimize the routing between Pblocks
A single Pblock should not occupy over 20 percent of the design resources
If so, try to make two Pblocks from logic at a lower level

4. UCF Syntax Pblocks are used to group logic Pblocks form a group
INST "usbEngine1" AREA_GROUP = "pblock_usbEngine1";
Area constraints form a range constraint
AREA_GROUP "pblock_usbEngine1“ RANGE=SLICE_X0Y60:SLICE_X43Y119;
AREA_GROUP (Area Group) is a design implementation constraint that enables partitioning of the design into physical regions for mapping, packing, placement, and routing.
1. AREA_GROUP is attached to logical blocks in the design, and the string value of the constraint identifies a named group of logical blocks that are to be packed together by mapper and placed in the ranges if specified by PAR. If AREA_GROUP is attached to a hierarchical block, all sub-blocks in the block are assigned to the group. Once defined, an AREA_GROUP can have a variety of additional constraints associated with it to control its implementation.
2. RANGE defines the range of device resources that are available to place logic contained in the AREA_GROUP, in the same manner ranges are defined for the LOC constraint.

5. Making a Pblock To create a Pblock
Select a level of hierarchy or a component from the Netlist window and use the popup menu > New Pblock
Select a block from the Hierarchy viewer and use the popup menu > New Pblock command
From a timing report, use the popup menu > New Pblock command
1. The first thing you need is to select a level of hierarchy or a component from the Netlist window. Right Click and select the New Pblock command in the pop up menu as shown in the screen shot here.   
2. To create a new Pblock, select a block from the Hierarchy viewer and use the popup menu > New Pblock command.
3. or from a timing report, use the popup menu > New Pblock command.
The New Pblock command creates a new Pblock in the Physical Constraints view, but does not create a rectangle in the Device view. You must pre-select logic for assignment to the new Pblock. If no logic is pre-selected, the command creates an empty Pblock. To create new Pblocks with or without pre-selected logic, select New Pblock from the popup menu.

6. Auto-create Pblock
From the horizontal toolbar use the Tools > Auto-create Pblocks command
If more modules exist than the total number of Pblocks specified, it will create Pblocks for the largest modules
PlanAhead enables automatic Pblock placement using the Auto-create Pblocks command. This method is used primarily to create top-level Pblocks to view the data flow of the design and to understand the relative size and relationship between the various logic modules in the design. Normally, the designer has some concept of the critical modules and circuitry in the design and begins floorplanning with those modules.
1. To run Auto-create Pblocks command, from the horizontal toolbar use the Tools>Auto-create Pblocks command. In the dialog box, review the options with which you can define the maximum number of Pblocks to create and specify the minimum Pblock size.
2. If more modules exist than the total number of Pblocks specified, it will create Pblocks for the largest modules.

7. Device Viewer Create or view Pblocks easily using the Device viewer.
The vertical toolbar has the following controls
Show/Hide I/O Nets
Show/Hide Bundle Nets
Show/Hide Loc Constraints
Show connections for selected instances
Draw Pblock
The Device viewer gives a graphical diplay of your design’s floorplan with the resources used on the FPGA. You can easily create Pblocks by selecting a portion on the FPGA.
<click>
The vertical toolbar provides you with different options with which you can draw aPlblock and control the net connectivity views and LOC constraints.

8. Pblock Properties
After selecting a Pblock use the popup menu > Pblock Properties command
Shows device utilization of Pblock
CLB
Block RAM
DSP slice
Number of clocks
Best way to determine
You can display various types of information with the Pblock Properties view.
1. To display or edit Pblock properties, select the Pblock and view the Pblock Properties view.
2. The Statistics tab of the Pblock Properties view displays content information about the Pblock.
The Statistics tab shows the following Pblock information:
• Physical Resources Estimates—A chart of each resource type in the device.
• Carry Statistics—The number of vertical carry chain logic objects assigned to the Pblock. It also displays the tallest carry chain assigned to the Pblock and the percentage of its height in relation to the Pblock height.
• Clock Report—Clock signals (Local, Global, and Resource) contained in the Pblock as well as the number of clocked instances on each clock.
• RPM Statistics—The number of Relatively Placed Macros (RPM) objects assigned to the Pblock. It also displays the tallest and widest RPM assigned to the Pblock and the percentage of its size in relation to the Pblock size.
• Clock Region Statistics—The utilization percentage of each clock region that the Pblock overlaps.
• Primitive Statistics—The number of each type of logical resource assigned to the Pblock.

9. Analyzing Connectivity
Use the Show Connectivity popup menu command to identify
Widely dispersed routing
Tightly clumped logic modules
Use Shift-click to select source and destination logic
Use the popup menu > Show Connectivity command
You can use this command sequentially to expand a cone of logic
The PlanAhead software has extensive logic expansion, selection and highlighting capabilities. These capabilities can be used to validate that modules are suitable to floorplan. For example, logic modules that connect to logic throughout the device may not be suitable for floorplanning, while tightly grouped and self-contained modules are suitable.
Routing congestion and timing inconsistency can be alleviated by floorplanning logic outside of
the critical logic areas, preventing logic from migrating into the critical areas.
1.Use the Show Connectivity popup menu command to identify, widely dispersed routing and tightly clumped logic modules.
2. Use Shift-click to select source and destination logic. Right-click and select the Show Connectivity popup menu command.
3. You can use the Show Connectivity command to highlight or select a cone of logic from any source net or logic object.

10. Analyzing Timing Results
Examine your timing results
Generated timing reports make it easy to display all or some paths that are failing to meet a timing constraint
Helps you see patterns
Simply select the paths to be displayed from the report or use Shift + click to select a group of paths
To remove, reselect the group and click the Hide All Timing Paths button from the vertical toolbar
After selecting a path use the popup menu > View Path Report command to see a more detailed timing report
When a timing path is selected, all the gates in the path are selected. The path properties window will show the timing information for each level of hierarchy.
If post-place and route placement has been loaded, the tool will show how the path was placed in the device.

11. Analyzing Timing Results with the Schematic
View critical paths with the Schematic viewer
Select the path(s) and use the popup menu > Schematic command
Helps you visualize the levels of hierarchy
Analyze logic modules for floorplanning
Create Pblocks from selected modules
Use the popup menu > Select Primitive Parents command to select the smallest modules containing all of the selected primitives
You can view the critical paths with the schematic viewer by selecting the paths and use the popup menu > schematic command.
1. This helps your to visualize the levels of hierarchy in your design.
2. Then analyze the logic modules that needs to be floorplan.
3. Create Pblock for that logic modules.
4. Use the popup menu > Select Primitive Parents command to select the smallest modules containing all of the selected primitives.

12. Visualizing Hierarchy
Hierarchy view displays logic hierarchy
Visualize relative size and location of selected logic in Hierarchy view
Easily select parent modules of selected logic to floorplan
Use the popup menu > Show Hierarchy command to view a selected module with this view
Note that this only shows size; it does not show how many signals are connected between the modules
Likewise, after selecting a component, use the popup menu > New Pblock command to assign the logic
The Hierarchy view displays the hierarchical relationship of the modules and the relative sizes. The selected logic module displays in the Hierarchy view, which is useful to visualize the module location and relative size prior to floorplanning. You can select modules directly from this view for floorplanning. Logic selected in other views is highlighted in the Hierarchy view.
1. You can easily select parent modules of selected logic to floorplan.
2. Use the popup menu > Show Hierarchy command to view a selected module with this view.
3. This will show only the size and does not show the signals that are connected between the modules.
4. Likewise, after selecting a component, use the popup menu > New Pblock command to assign the logic.

13. Case Study Design has been implemented with no area constraints
Import the design into the PlanAhead™ software and perform a timing analysis
Display all of the paths that are failing to meet timing to get ideas
Note the hierarchical blocks that are part of the failing paths
In this example, note that there are long routing delays between some of the block RAMs
This is an example using floorplanning for Timing Closure. The design has been implemented with no area constraints.
Only post implementation timing numbers identify what logic is failing timing. After the design has been run through implementation, and the design fails timing, load the results into the PlanAhead tool.
Display all of the paths that are failing to meet timing to get ideas.
Note the hierarchical blocks that are part of the failing paths.
 In this example, the block RAMs with the critical paths are spread out over more of the chip then they need to be. Floorplanning can be used to generate a tighter placement. The timing problem occurs in the paths between block RAM. These paths are good candidates for floorplanning.

14. Case Study Failing paths displayed with the Schematic viewer
Confirmed from the timing reports that most of these paths can be constrained within a few area constraints
In this case, usbEngine1 is a good candidate, but there may be others
Start off by loading the critical paths into the schematic. The schematic will show which gates are involved in the critical path and in which hierarchy the gates are located. You can trace the logic around the critical gates in the schematic to see how the non-critical logic is structured.
 The floorplan should constraint at least the timing critical paths between block RAMs inside usbEngine1. So far, usbEngine1 appears to be a good candidate for floorplanning. If usbEngine1 is a large portion of the chip, instead we would try to floorplan the four levels of sub hierarchy that contain the critical path.

15. Case Study Placement reviewed in the Device view
Timing critical nets and logic in green (20% of design)
Note the use of block RAM
Is there anything wrong?
Note the pin layout
Answer 1:
Block RAMS are fixed into separate columns. So any time you have a hierarchical component that uses more block RAM or DSP slices than are placed into one column, you may have timing problems due to the routing to and from separate columns.
Answer 2:
Long routes to pins.
This brings to mind the question: Was a good pinout made? If it is too late to re-assign pins, then the logic will need to be placed near the pins.
If this slide does not show up well, you can refer to page 25 of the Floorplanning Methodology Guide or ask the instructor to project this slide on the board.

16. Case Study
Top-level floorplan examined (this is just Pblocks with no area constraints)
These will have to be made by the user and are based on the design hierarchy
The white box is usbEngine1
Note the green lines
These are the connections from logic to I/O pins
Is there anything wrong?
Note the red lines
They represent the greatest concentration of routes between hierarchical blocks
Where should each Pblock go? 3 4
Answer 1:
Long routes to pins.
Answer 2:
Pblock 1 is okay (it is near its I/O pins). Pblock 2 is also okay.
Pblock 3 needs to be centrally located because it is the most popular (communicates with the other Pblocks the most).
Pblock 4 needs to be lower (closer to its I/O pins).
Pblock 5 needs to be in the upper-left corner of the die. This will put it near its I/O pins and next to Pblock 3.
Pblock 6 could be placed anywhere (no I/O pins), but it needs to be next to Pblock 3.
Note: If you are going to make all of these area constraints, remember to make sure that Pblock 3 touches with all of the other Pblocks (remember it needs to communicate with all of the others). If other Pblocks communicate with each other, it is also recommended they touch.
In the end, if you did not want to make all of these Pblocks and area constraints, you could possibly get by with just an area constraint around usbEngine1 (assuming that was the only block that had timing errors).
If this slide does not show up well, you can refer to page 25 of the Floorplanning Methodology Guide or ask the instructor to project this slide on the board. 2 5 6 1

17. Case Study
If all the timing errors were only in usbEngine1, then an area constraint for Pblock 5 might be able to be made
Saves some work
The block RAMs and DSP slices within usbEngine1 could also be placed in the upper left corner of the die
This would in effect force the tools to place the logic closer to its I/O pins 2 1 3 4 6 5
The implementation shows the timing errors were only in usbEngine1, then an area constraint for Pblock-5 will be done.
The usbEngine1 could also be placed in the upper left corner of the die, which would place the logic closer to the I/O pins.

18. Case Study There were also timing errors in the usbEngine0 component
In the end, this also required similar floorplanning
So the final solution is shown here
This design has two copies of the same component: usbEngine1 and usbEngine0. Implementation has shown that there is a timing problem with usbEngine1, which will likely appear in usbEngine0 as well. You will need to solve the timing problems of each block separately. Consider both USB blocks as two separate timing critical hierarchies, and floorplan each hierarchy separately.

19. UCF Syntax The following constraints are the output of this exercise
INST "usbEngine1" AREA_GROUP = "pblock_usbEngine1";
AREA_GROUP "pblock_usbEngine1" RANGE=SLICE_X0Y60:SLICE_X43Y119;
AREA_GROUP "pblock_usbEngine1" RANGE=DSP48_X0Y24:DSP48_X2Y47;
AREA_GROUP "pblock_usbEngine1" RANGE=RAMB18_X0Y24:RAMB18_X2Y47;
AREA_GROUP "pblock_usbEngine1" RANGE=RAMB36_X0Y12:RAMB36_X2Y23;
PlanAhead creates a construct that enables you to constrain any subset of netlist hierarchy to a region on the chip. They are created using the New Pblock and Assign to Pblock commands. The Pblocks are turned into AREA_GROUP constraints in the UCF to guide implementation and they keep the level(s) of hierarchy to various regions on the chip.

20. List of Questions (Revisited)
In hindsight, maybe there could have been a few more questions
Were proper pin planning decisions made?
Is there any central logic that needs to be placed in the middle of the die?
Are all my area constraints touching appropriately?
Should any of my area constraints be used to place logic near dedicated hardware (such as GTs, the PCI core, or memory controllers, for example)?
In hindsight, maybe there could have been a few more questions.
Were proper pin planning decisions made?
 Is there any central logic that needs to be placed in the middle of the die?
 Are all my area constraints touching appropriately?
 Should any of my area constraints be used to place logic near dedicated hardware (such as GTs, the PCI core, or memory controllers, for example)?

21. Summary
Pblocks
Are used to group logic
Support a user-programmable utilization
90%+ for low speed
70–87% for high speed
There are a number of utilities in the PlanAhead software that can help you make good area constraints
Hierarchy viewer, Schematic viewer, and Timing Report generator
Automatic Pblock assignment and placement

22. More Information
To learn more, visit the PlanAhead tool web site
Articles, documentation, white papers, and training enrollment
User Guide
PlanAhead Software Tutorial, Design Analysis and Floorplanning for Performace, UG676
Floorplanning Methodology Guide, UG633
View the PlanAhead tool video demonstrations
Quick Tour of the PlanAhead Design and Analysis Tool
I/O pin planning with PinAhead Technology
Improve Design Performance with the PlanAhead Design and Analysis tool
PlanAhead User Guide
From the Project Manager: Help > User Guide > PlanAhead User Guide
Chapter 10, Analyzing Implementation Results
Chapter 11, Floorplanning the Design
Floorplanning Methodology Guide
From the Project Manager: Help > Methodology Guides > Floorplanning
PlanAhead Tutorials
From the Project Manager: Help > PlanAhead > Tutorials > Design Analysis and Floorplanning for Performance

23. Where Can I Learn More? Xilinx Education Services courses
Xilinx tools and architecture courses
Hardware description language courses
Basic FPGA architecture, Basic HDL Coding Techniques, and other free Videos!

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