1. ECE 368: CAD-Based Logic Design Lecture Notes # 5
Sequential Circuit (Finite-State Machine) Design
SHANTANU DUTT
Department of ECE
University of Illinois, Chicago
Phone: (312) :
URL:

2. Finite State Machine (FSM) Design
• FSMs are different from counters in the sense that they have external
I/Ps, and state transitions are dependent on these I/Ps and the current
state.
• Example : Problem Statement
There is a bit-serial I/P line. Design an FSM that outputs a ‘0’
if an even # of 1’s have been received on the I/P line and the
outputs a ‘1’ otherwise.
Note : If a synchronous sequential circuit is being designed, the counting
of the # of 1s occur every clock cycle.
FSM x
O/p y
CLK
CLK x
# of 1s
even
(0)
odd
(1)
(2)
(3)
Tlogic + Tsetup
Sampling
instances

3. Approach to determining states of an FSM:
First determine the min # of useful information classes about past i/ps required to solve the problem (requires analytical thinking about the problem)
Each info class  a potential state
From this 1st cut at possible states, determine if there are well-defined transitions from each state for all possible i/p values.
If so then these states can be the final states; otherwise some states may need to be refined into multiple states to achieve well-defined transitions (see FSM word prob. 1).
• In this problem, only 2 classes of information are reqd: whether an even # of 1s have been received so far, or an odd # of 1s have been received so far & there are well-defined transitions between them. Thus these 2 classes become 2 states.
Solution 1: (Mealy)
0/0
Even
Odd
1/1
1/0
0/1
Reset
Output
Input
Transition
Arc
O/P is dependent
on current state and
input in Mealy
Mealy Machine: Output is associated with the state transition, and appears before the state transition is completed (by the next clock pulse).
Even 1
Reset
[0]
Odd
[1]
Output
Input
Output is
dependent only
on current state
Solution 2: (Moore)
Moore Machine: Output is associated
with the state and hence appears
after the state transition take place.

4. Determining a Reset State:
A reset state is a state the the FSM (seq ckt) should be in when it is just powered on.
In other words, a reset state is a state the FSM should be in, when it has recvd no i/ps
Based on the above definition, decide if any of the states determined so far can be a reset state. E.g., in the parity detector problem, the even state qualifies to be the reset state, as in the reset state no i/ps recvd  zero 1’s recvd  even # of 1’s recvd  it can be the even state
If not, then need to have a separate reset state, and have the correct transitions from this state to the other states (depending on the problem solved by the FSM).
Solution 1: (Mealy)
0/0
Even
Odd
1/1
1/0
0/1
Reset
Output
Input
Transition
Arc
O/P is dependent
on current state and
input in Mealy
Even 1
Reset
[0]
Odd
[1]
Output
Input
Output is
dependent only
on current state
Solution 2: (Moore)
Moore Machine: Output is associated
with the state and hence appears
after the state transition take place.
Mealy Machine: Output is associated
with the state transition, and appears
before the state transition is completed
(by the next clock pulse).

5. Moore Machine Model Mealy Machine Model FFs n CLK Output Logic m2
Next State
Comb. m1
External
I/Ps
External Outputs
FFs
External I/Ps
External O/Ps m1 m2 n
Comb.
Logic
CLK
even 
odd
Mealy Machine Model
Moore Machine Model
Time t : Even I/P  = propagation delay of logic of Mealy M/C
2 = propagation delay of O/P
logic unit of Moore M/C t
t+
t+TCLK
t+TCLK+2
Even
x=1
O/P=0
Odd
O/P=1
(Moore)
O/P=1
(Mealy)

6. State Transition Table
(Even-Parity Checker)
Even State: 0 ; Odd State: 1; State Variable A
Present
State
Next
State
Moore
O/P
Mealy
O/P
D-FF
Excit.
T-FF
Excit.
Input
A x A y y DA TA
Input variables
to comb. logic
Output functions Q FF
N.S. & O/P
Logic
CLK x y2 A DA
FFs y1
N.S.
Logic
O/P DA A Q x
DA= Ax (same for Moore
and Mealy);
TA= x (same for Moore
y1 = A for Moore
y2 = Ax for Mealy Or

7. Mealy Moore Reset Reset 1/1 1/0 1 1 0/1
0/0
State=0
Even
Reset
State=0
Even
1/1
[0]
1/0 1 1
State=1
Odd x
N.S.
Logic
State=1
Odd
[1]
0/1 Q D-
Mealy Q FF D
Moore
S.T. is complete.
CLK
Assume single bit state information stored in a D-FF
State Transition
is occurring
State Transition
is occurring
S.T. is complete.
CLK x D Q
(state)
even
odd
even
even
odd
odd y2
(Mealy O/P) y1
Moore O/P)

8. DA= Ax ; TA= x; y1 = A for Moore; y2 = Ax for Mealy
Moore M/C Implementation
a) D-FF
b) T-FF x
A y2 A y2
T Q
D Q
x=1
CLK R Q R Q
CLK
Reset
Reset
Moore O/P is synchronized with clock.
Mealy M/C Implementation y1 x y1 1
T Q A
D Q
x=1
CLK R Q R Q
CLK
Reset
Reset
b) T-FF
a) D-FF
Mealy O/P is not synchronized with clock.
Note: Here Moore and Mealy state transition
function is the same. Will not always be the case.

9. Difference Between Mealy and Moore Machine
Mealy Moore
(1) O/Ps depend on the present O/Ps depend only on the
state and present I/Ps present state
(2) The O/P change asyn Since the O/Ps change
-chronously with the when the state changes,
enabling clock edge and the state change is
synchronous with the
enabling clock edge, O/Ps
change synchronously
with this clock edge
(3) A counter is not a Mealy A counter is a Moore
machine machine
(4) A Mealy machine will have
the same # or fewer states
than a Moore machine

10. Behavioral FSM Descriptions in VHDL – 1st Cut
entity fsm1_1 is
port (x, reset:in bit; y: out bit:=`0’)
end entity fsm1_1
architecture behav of fsm1_1 is
type states is (even, odd);
begin
state_mc: process (x, reset) is
variable curr_state, next_state: states := even;
-- initial state is reset state
if reset = ‘1’ then curr_state := even; y <= ‘0’;
else
case curr_state is
when even => y <=`0’; -- assert output
-- next determine transition based on input
if x=`1’ then next_state := odd;
else next_state := even; end if;
when odd => y <= `1’; -- assert output
if x=`1’ then next_state := even;
else next_state := odd; end if;
end case;
curr_state := next_state;
end if;
end process state_mc;
end architecture behav;
Even 1
Reset
[0]
Odd
[1]
Moore machine
FFs y
N.S.
Logic
O/P Q x
C.S.
Simple very high-level behavioral description w/o timing (no clock, no delays)
Checks only the high-level FSM logic
No parallelism
If timing and/or parallelism of the underlying hardware is desired we need to introduce clocks, delays and multiple processes

11. Behavioral FSM Descriptions in VHDL – 2nd Cut
architecture behav of fsm1_2 is
type states is (even, odd);
begin
state_mc: process is
variable curr_state, next_state: states := even; -- reset state
wait until (clk’event and clk=`1’) or (reset=`1’);
if reset = ‘1’ then curr_state := even; y <= `0’ after 2 ns;
else
-- note need of curr_state to be variable for immediate effect
case curr_state is
when even => y <=`0’ after 2 ns; -- assert outputs
-- next determine transition based on input
if x=`1’ then wait for 2 ns; next_state := odd;
else wait for 2 ns; next_state := even; end if;
when odd => y <= `1’ after 2 ns; -- assert outputs
if x=`1’ then wait for 2 ns; next_state := even;
else wait for 2 ns; next_state := odd; end if;
end case;
curr_state := next_state;
end if;
end process state_mc;
end architecture behav;
Even 1
Reset
[0]
Odd
[1]
Moore machine
FFs y
N.S.
Logic
O/P Q x
C.S.
entity fsm1_2 is
port (x, clk, reset:in bit; y: out bit:=`0’)
end entity fsm1_2
Problem w/ the description: The N.S. logic is simulated only on the clock edge. Actually, it
should be simulated anytime x or C.S. changes. The latter happens in the code but not the former.

12. Behavioral FSM Descriptions in VHDL – Final Cut
General solution to behavioral description of a system (described in an arch) – when to have multiple processes:
-- If a design has different components, each operating or triggered w/ different timing events, then separate them into individual processes.
-- In other words a single process should not describe multiple components triggered by different timing events
-- Furthermore if signal assignments to, say, signal X, in a process should affect the rest of the logic in it in the current iteration and X cannot be made a variable (if it is also an o/p of the process, e.g., when it is an i/p signal of another process), separate out the X-dependent logic as a separate process
-- In a Moore machine, we have 3 modules, FFs, N.S. logic and O/P logic. FF is triggered by the clock +ve edge. Its o/p C.S. triggers the O/P logic; so it is also ultimately triggered by the clock. The N.S. logic is triggered by C.S. and x, where x has no relation to the clock.
-- So a possible breakup is Process 1: FFs + O/P Logic and Process 2: N.S. Logic. But not a good idea as:
-- C.S. needs to be a signal i/p to the N.S. Logic and FF processes to communicate
-- Since the O/P Logic depends on C.S., if it is in the same process as the FF, there will not be any effect from the FF to the O/P Logic modules in the current iteration (in other words, combined FF+O/P process will need to be simulated more times (i.e., it has to be activated by more events, which may or may not happen) to propagate final values to o/p of O/P module). So separate out the O/P Logic as a 3rd process
-- Large processes resulting from the above partitioning methodology may be further broken up functionally (i.e., by functional modules, e.g., ALU and Register File in a Datapath process of a CPU) and/or if some parallelism of the underlying hardware is desired to be simulated and/or communication between these modules need to be simulated
FFs y
N.S.
Logic
O/P Q x
C.S.
Process 2
Process3
Process 1
clock
X <= …..
Y <= X nand Z;
Process A
Process B

13. Behavioral FSM Descriptions in VHDL – Final Cut
architecture behav of fsm1_3 is
type states is (even, odd);
signal next_state, curr_state: states := even;
begin
ns_proc: process (curr_state, x) is
case curr_state is
when even => if x=`1’ then next_state <= odd after 2 ns;
else next_state <= even after 2 ns; end if;
when odd => if x=`1’ then next_state <= even after 2 ns;
else next_state <= odd after 2 ns; end if;
end case;
end process ns_proc;
ff_proc: process is
wait until (clk’event and clk=`1’) or (reset=`1’);
if reset = ‘1’ then curr_state <= even;
else curr_state <= next_state; end if;
end process ff_proc;
op_proc: process (curr_state) is
when even => y <=`0’ after 2 ns; -- assert outputs
when odd => y <= `1’ after 2 ns;
end process op_proc;
end architecture behav;
Even 1
Reset
[0]
Odd
[1]
Moore machine
Process3
FFs y
N.S.
Logic
O/P Q x
C.S.
Process 2
Process 1
clock
Note: When all processes block, sim. time
is advanced by the fictitious delta time or min. delay across signals, resulting in assigned signal values appearing and causing corresponding processes to unblock (those w/ wait statements dependent on these signals).
entity fsm1_3 is
port (x, clk, reset:in bit; y: out bit:=`0’)
end entity fsm1_3

14. Behavioral FSM Descriptions in VHDL– First Cut
architecture behav of fsm2_1 is
type states is (even, odd);
begin
state_mc: process is
variable next_state, curr_state: states := even; -- reset state
wait until (clk’event and clk=`1’) or (reset=`1’);
if reset = ‘1’ then curr_state := even;
else curr_state := next_state; end if;
case curr_state is
when even => if x=`1’ then y <= `1’ after 2 ns;
wait for 2 ns; next_state := odd;
else y <= `0’ after 2 ns;
wait for 2 ns; next_state := even after 2 ns; end if;
-- note: above times are arbitrary; just for e.g.
when odd => if x=`1’ then y <=`0’ after 2 ns;
wait for 2 ns; next_state := even after 2 ns;
else y <= `1’ after 2 ns;
wait for 2 ns; next_state := odd after 2 ns;
end if;
end case;
end process state_mc;
end architecture behav;
Mealy Machine
0/0
Even
Odd
1/1
1/0
0/1
Reset
Transition
Arc x y2
N.S. & O/P
Logic Q FF
C.S.
N.S.
CLK
entity fsm2_1 is
port (x, clk, reset:in bit; y: out bit:=‘0’)
end entity fsm2_1
Problem w/ the description: The N.S. & O/P logic is simulated only on the clock edge. Actually, it should be simulated anytime x or C.S. changes. The latter happens but not the former.

15. Behavioral FSM Descriptions in VHDL– Final Cut
architecture behav of fsm2_2 is
type states is (even, odd);
signal next_state, curr_state: states := even;
begin
ns_op_proc: process (x, curr_state) is
case curr_state is
when even => if x=`1’ then y <= `1’ after 2 ns;
next_state <= odd after 2 ns;
else y <= `0’ after 2 ns; next_state <= even after 2 ns; end if;
-- note: above times are arbitrary; just for e.g.
when odd => if x=`1’ then y <=`0’ after 2 ns;
next_state <= even after 2 ns;
else y <= `1’ after 2 ns; next_state <= odd after 2 ns;
end if;
end case;
end process ns_op_proc;
ff_proc: process is
wait until (clk’event and clk=`1’) or (reset=`1’);
if reset = ‘1’ then curr_state <= even;
else curr_state <= next_state; end if;
end process ff_proc;
end architecture behav;
Mealy Machine
0/0
Even
Odd
1/1
1/0
0/1
Reset
Transition
Arc x y2
N.S. & O/P
Logic Q FF
C.S.
N.S.
CLK
entity fsm2_2 is
port (x, clk, reset:in bit;
y: out bit:=‘0’)
end entity fsm2_2

16. Another example: A simple vending machine
Here is how the control is supposed to work. The vending machine delivers
a package of gum after it has received 15 cents in coins. The machine has a single
coin slot that accepts nickels and dimes, one coin at a time. A mechanical sensor
indicates to the control whether a dime or a nickel has been inserted into the coin slot.
The controller’s output causes a single package of gum to be released down a chute
to the customer.
One further specification: We will design our machine so it does not give
change. A customer who pays with two dimes is out 5 cents!
Coin
Sensor
Vending
Machine
FSM
Gum
Release
Mechanism
Open
CLK
Reset
Reset (ext.)
Timer OR
time_out
Vending Machine block diagram
States: 0C
15C
10C 5C

17. Moore and Mealy machine state diagrams for the vending machine FSM
— The figure below show the Moore and Mealy machine state transition diagrams.
Reset / 0
)/0
0 cent
[0]
5 cent
10 cent
15 cent
[1]
Moore machine
Reset
N+D N D
)/0
Reset
0 cent
Reset / 0
N / 0
5 cent
D / 0
D/1
N / 0
10 cent
N+D/1
15 cent
Reset / 1
Mealy machine
Moore and Mealy machine state diagrams for the vending machine FSM

18. Behavioral VHDl description of Moore vending machine controller
entity vend_moore is
port(N, D, ext_reset, clk: in bit;
open1:inout bit);
end entity vend_moore;
architecture behav of vend_moore is
type states is (S0, S5, S10, S15);
signal next_state, curr_state: states := even;
signal reset, time_out : bit := `0’;
begin
reset <= ext_ reset or time_out after 2 ns;
-- concurrent signal assignment statement
timer: process is
wait until open1 = `1’;
time_out = `1’ after 20 sec;
wait for 20 sec;
time_out = `0’ after 10 ns;
-- timeout signal is high for 10 ns;
if open1 = `1’ then wait until open1 = `0’;
end process timer;
ff_proc: process is
begin
wait until (clk’event and clk=‘1’) or ( reset=`1’);
if reset = ‘1’ then curr_state <= S0 after 1 ns;
else curr_state <= next_state after 1 ns; end if;
end process ff_proc;
op_proc: process (curr_state) is
case curr_state is
when S0 => open1 <=` 0’ after 2 ns;
when S5 => open1 <= `0’ after 2 ns;
when S10 => open1 <=` 0’ after 2 ns;
when S15 => open1 <= `1’ after 2 ns;
end case;
end process op_proc;
Timer
proc
o/p logic FF
NS logic
process
reset <= ext_ reset or time_out after 2 ns;
next_state
curr_state
open1
time_out N D
reset
clk
ext_reset
entity vend_moore
Arch. behav
Reset
Moore
machine
0 cent
[0]
5 cent
10 cent
15 cent
[1]
N+D N D
)/0

19. Behavioral VHDl description of Moore vending machine controller
ns_proc: process (N, D, curr_state) is
case curr_state is
when S0 =>
if N=1 then next_state <= S5 after 2 ns; elsif D=1 next_state <= 10 after 2 ns;
else next_state <= S0 after 2 ns;
end if;
when S5 =>
if N=1 then next_state <= S10 after 2 ns; elsif D=1 next_state <= S15 after 2 ns;
else next_state <= S5 after 2 ns;
when S10 =>
if N=1 or D=1 then next_state <= S15 after 2 ns;
else next_state <= S10 after 2 ns;
when S15 =>
next_state <= S15 after 2 ns;
end case;
end process ns_proc;
end architecture behav;
0 cent
[0]
5 cent
10 cent
15 cent
[1]
Reset
N+D N D
)/0
Reset
Moore
machine

20. —State transition table for Moore and Mealy M/C
—State transition table for Moore and Mealy M/C.(Next state also gives D-FF
excitation).
Present State Inputs Next State Moore Output Mealy Output
Q1 Q D N Q1+ Q Open Open
x x x x
Q+ = D
Q Q+ D
Encoded vending machine state transition table. Note: Do not have to design
for the reset input if FFs have a direct reset inputs. Make sure though that reset state is
encoded as all 0’s if possible; otherwise need FFS w/ asynch. reset as well as set inputs

21. Implementation using D-FFs 00 01 11 10
Q1Q0 DN 00 01 11 10
Q1Q0 DN 00 01 11 10
Q1Q0 DN
x x x x
x x x x
x x x x
K-map for Open (Moore)
K-map for D1
K-map for D0 00 01 11 10
Q1Q0 DN
D1 = Q1 + D + Q0·N
OPEN = Q1·Q0
OPEN = Q1·Q0 + D·Q0 + D·Q1 + N·Q1
Moore
x x x x
Mealy
K-map for Open (Mealy)

22. Similarly, a Mealy implementation; only the OPEN function changes. D Q
CLK
Similarly,
a Mealy
implementation;
only the OPEN
function changes. R Q N
OPEN
Reset N Q0 D0 Q0
D Q
CLK Q1 R Q N
Reset Q1 D
Vending machine FSM implementation based on D flip-flops(Moore).

23. Implementation using J-K FFS
J-K Excitation
Q1 Q D N Q1+ Q J1 K J0 K0
x x
x x
x x
x x x x x x
x x 0
x x 1
x x 0
x x
x x
x x
x x 0
x x 0
x x 0
x x x x x x
Q Q+ J K x x
x 1
x 0
Remapped next-state functions for the vending machine example.

24. 00 01 11 10
Q1Q0 DN 00 01 11 10
Q1Q0 DN
x x
x x
x x
x x
x x x x
x x x x
x x
x x
K-map for J1
K-map for K1 00 01 11 10
Q1Q0 DN 00 01 11 10
Q1Q0 DN
x x
x x
x x
x x
x x x x
x x x x
x x
x x
K-map for J0
K-map for K0
K-maps for J-K flip-flop implementation of vending machine.
J1 = D + Q0·N K1 = 0

25. J-K flip-flop implementation for the vending machine example (Moore).Q0 Q1
J Q
CLK D Q K R
OPEN N Q1 D Q0
J Q
CLK Q K R N
Reset
J-K flip-flop implementation for the vending machine example (Moore).
Similarly, a Mealy implementation; only the OPEN function changes.

26. Basic Steps in the FSM Design Procedure
1. Understand the problem and the different information classes
(minimal number) required to solve it. Also make sure there are
well-defined transitions possible between these classes; otherwise
break down some or all classes into smaller classes to get well-defined
transitions.
2a. Convert these information classes into distinct states, and
determine the state transition diagram of the FSM. Determine reset state.
2b Optional: Perform state minimization
3a. Encode states in binary, and obtain state transition table and FF
excitation (for desired FF type).
3b Optional: Perform state assignment for minimizing logic.
4. Minimize the FF excitation functions and output functions
(using K-Maps, for example) and implement the FSM using these
FFs and logic gates (or MUXes, PLAs, etc.) that implement the
output and FF excitation functions.

27. FSM Word Problem 1:
• Design a system that outputs a ‘1’ whenever it receives a multiple
of 3 # of 1’s (i.e., 0, 3, 6, 9, etc. # of 1’s) on a serial input line x.
— Relevant information classes needed to solve the problem:
(A) A multiple of 3 # is received.
(B) A non-multiple of 3 # is received.
Questions to consider:
(1) How do we go from (A)(B)
Ans.: If a ‘1’ is received
(2) How do we go from (B)(A)
Ans.: Not clear. Need to split up (B) further into
(B1): 3y+1 # of 1’s received.
(B2): 3y+2 # of 1’s received.
Where y is an integer  0.

28. Note: (A): is 3y+0 = 3y # of 1’s received.
• Now the transitions between the3 classes of information is clear:
(A)  (B1)  (B2)  (A)
1 received
1 received
1 received
• Hence these classes of information can be considered states of
the required as states of the required FSM:
These 3 states can be represented by 3y+I, i = 0,1,2
i=0
i=1
i=2
Reset
0/1
0/0
1/0
1/1 00 10 01
Mealy Machine
Input
Output
i=2
[0]
i=1
i=0
[1]
Reset 1
Moore Machine

29. • Design a system that outputs a ‘1’ whenever it receives:
FSM Word Problem 2:
• Design a system that outputs a ‘1’ whenever it receives:
(a) A multiple of 3 # of 1’s AND (b) A non-zero even # of 0’s
E.g., ((0,2) , (3,2) , (3,4) , (6,2) ,···)
— Relevant classes of information:
- For # of 1’s: 3y+i, i = 0,1,2
[3 classes]
- For # of 0’s: 2z+j, j = 0,1
For j = 0, we need to distinguish between zero (z = 0)
and non-zero (z > 0) # of 0’s
- Thus we have 3 classes:
2z+0, z = 0 ( 0 )
2z+0, z > 0 ( non-zero even )
2z ( odd )
# of 1’s
# of 0’s

30. The relevant # of 1’s can be represented by i = { 0, 1, 2 }
( # of 1’s = 3y+i )
— The relevant # of 0’s can be represented by j= { 00 , 0>0 , 1 }
( # of 0’s = 2z+j ) where the subscript of the 0 indicates whether
z=0 or z>0.
— Since at any point time, a certain # of 1’s and # of 0’s will have
been received, the state of the system will be given by
a combination of relevant # of 1’s and # of 0’s.
— There are 9 combinations:
{ 0, 1, 2, } X { 00, 0>0, 1 } = (0,00), (0,0>0), (0,1), (1,00), (1,0>0),
(1,1), (2,00), (2,0>0), (2,1) 
# of 1’s # of 0’s
Cartesian
Product

31. (0,00)
(0,0>0)
(1,00)
(0,1)
(2,00)
(1,1)
(2,1)
(1,0>0)
(2,0>0)

32. Note: 0>0  2z+j, j = 0 z > 0 (0,00) (0,0>0) (1,00) (0,1)
Reset
(0,00)
0/0
1/0
1/0
(0,0>0)
(1,00)
0/0
1/0
0/0
0/1
1/0
(0,1)
(2,00)
(1,1)
1/0
0/0
0/0
1/0
(2,1)
0/0
(1,0>0)
1/1
0/0
1/0
0/0
(2,0>0)
1/0