1. Delays in Verilog Programmable Logic Design (40-493) Fall 2001
Computer Engineering Department
Sharif University of Technology
Maziar Gudarzi

2. Introduction Delays are crucial in REAL simulations Delay Models
Post-synthesis simulation
Post-layout simulation
FPGA counter-part: Post-P&R simulation
Delay Models
Represent different physical concepts
Two most-famous models
Inertial delay
Transport delay

3. Delay Models
Delays in Verilog

4. Delay Models Inertial Delay
The inertia of a circuit node to change value
Abstractly models the RC circuit seen at the node
Different types
Input inertial delay
Output inertial delay

5. Delay Models Transport Delay
Represents the propagation time of signals from module inputs to its outputs
Models the internal propagation delays of electrical elements

6. Delay Types
Delays in Verilog

7. Delay Types Rise Delay Fall Delay Turn-Off Delay
Min/Typ/Max Delay values

8. Delays in Gate-Level Modeling
Delays in Verilog

9. Delays in Gate-Level Modeling
Delay are shown by # sign in all verilog modeling levels
Inertial rise delay
Inertial fall delay
Inertial turn-off delay
and #(rise_val, fall_val, turnoff_val) a(out,in1, in2)

10. Delays in Gate-Level Modeling (cont’d)
If no delay specified
Default value is zero
If only one value specified
It is used for all three delays
If two values specified
They refer respectively to rise and fall delays
Turn-off delay is the minimum of the two

11. Delays in Gate-Level Modeling (cont’d)
Min/Typ/Max Values
Another level of delay control in Verilog
Each of rise/fall/turnoff delays can have min/typ/max values
not #(min:typ:max, min:typ:max, min:typ:max) n(out,in)
Only one of Min/Typ/Max values can be used in the entire simulation run
It is specified at start of simulation, and depends to the simulator used
Typ delay is the default

12. Delays in Dataflow Modeling
Delays in Verilog

13. Delays in Dataflow Modeling
Regular Assignment Delays
assign #delay out = in1 & in2;
As in Gate-Level Modeling the delay is output-inertial delay

14. Delays in Dataflow Modeling (cont’d)
Implicit Continuous Assignment Delay
wire #delay out = in1 & in2;

15. Delays in Behavioral Modeling
Delays in Verilog

16. Delay in Behavioral Modeling

17. Today Summary Delays Models Types Delays in Verilog Inertial/Transport
Rise/Fall/Turn-off
Min/Typ/Max Values
Delays in Verilog
Gate-Level Modeling
Dataflow Modeling
Behavioral Modeling

18. Complementary Notes Assignment 6 Lab. Final Project Chapter 8:
All 6 Exercises with ModelSim (submit the Verilog source codes to
Design appropriate test-benches to exhaustively test the results and report the errors
Due date: Saturday, Day 15th
Lab. Final Project
Announce your group members today
Start your work

19. Complementary Notes (cont’d)
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